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clk: rockchip: rk3399: fix up some regs description error

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Change-Id: Ia992b20f13ba7037b93fcd2fbd67a4d6b3fd1266
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2018-07-25 10:30:28 +08:00
committed by Tao Huang
parent 5b94552057
commit eb3075d48d
2 changed files with 11 additions and 12 deletions
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21
drivers/clk/rockchip/clk-rk3399.c
View File

@@ -185,8 +185,8 @@ PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "dummy_cpll", "gpll", "npl
*/
PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "dummy_cpll", "gpll",
"npll" };
PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p) = { "dummy_vpll", "dummy_cpll", "gpll",
"xin24m" };
PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = { "dummy_vpll", "dummy_cpll", "gpll",
"gpll" };
PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
"dummy_cpll", "gpll" };
@@ -239,8 +239,8 @@ PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
*/
PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "cpll", "gpll",
"npll" };
PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p) = { "dummy_vpll", "cpll", "gpll",
"xin24m" };
PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = { "dummy_vpll", "cpll", "gpll",
"gpll" };
PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
"cpll", "gpll" };
@@ -809,7 +809,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(2), 7, GFLAGS),
GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
@@ -938,7 +938,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
RK3399_CLKGATE_CON(5), 3, GFLAGS),
COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
RK3399_CLKSEL_CON(14), 12, 3, DFLAGS,
RK3399_CLKGATE_CON(5), 4, GFLAGS),
GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
@@ -1182,9 +1182,8 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(29), 12, GFLAGS),
/* hdcp */
COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 12, GFLAGS),
COMPOSITE_NOGATE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS),
COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 3, GFLAGS),
@@ -1267,7 +1266,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(106), 0,
&rk3399_dclk_vop0_fracmux, 0),
COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 14, GFLAGS),
@@ -1304,7 +1303,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(107), 0,
&rk3399_dclk_vop1_fracmux, 0),
COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 15, GFLAGS),

2
include/dt-bindings/clock/rk3399-cru.h
View File

@@ -442,7 +442,7 @@
#define SRST_A_ADB400_GIC2COREB 40
#define SRST_A_ADB400_COREB2GIC 41
#define SRST_P_DBG_B 42
#define SRST_L2_B_T 43
#define SRST_L2_B_T 44
#define SRST_ADB_B_T 45
#define SRST_A_RKPERF_B 46
#define SRST_PVTM_CORE_B 47