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rk2928: a720 init

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This commit is contained in:
kfx
2012-08-19 15:18:44 +08:00
parent 21d650142f
commit ebe214e010
12 changed files with 1661 additions and 2 deletions
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381
arch/arm/configs/rk2928_a720_defconfig Normal file
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@@ -0,0 +1,381 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZO=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=1
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
CONFIG_ASHMEM=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_SLUB_DEBUG is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_RK2928=y
CONFIG_RK_DEBUG_UART=0
CONFIG_MACH_RK2928_A720=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_COMPACTION=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_WAKELOCK=y
CONFIG_PM_RUNTIME=y
CONFIG_SUSPEND_TIME=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_INET_ESP=y
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_H323=y
CONFIG_NF_CONNTRACK_IRC=y
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
CONFIG_NF_CONNTRACK_PPTP=y
CONFIG_NF_CONNTRACK_SANE=y
CONFIG_NF_CONNTRACK_SIP=y
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
CONFIG_NETFILTER_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
CONFIG_NF_CONNTRACK_IPV4=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=y
CONFIG_IP_NF_MATCH_ECN=y
CONFIG_IP_NF_MATCH_TTL=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_TARGET_REJECT_SKERR=y
CONFIG_IP_NF_TARGET_LOG=y
CONFIG_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_MANGLE=y
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y
CONFIG_NF_CONNTRACK_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_TARGET_LOG=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
CONFIG_IP6_NF_MANGLE=y
CONFIG_IP6_NF_RAW=y
CONFIG_BRIDGE=y
# CONFIG_BRIDGE_IGMP_SNOOPING is not set
CONFIG_PHONET=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_U32=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_ACT_GACT=y
CONFIG_NET_ACT_MIRRED=y
CONFIG_BT=y
CONFIG_BT_L2CAP=y
CONFIG_BT_SCO=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIBCM4325=y
CONFIG_BT_AUTOSLEEP=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_RFKILL=y
CONFIG_RFKILL_RK=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_RKNAND=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_MISC_DEVICES=y
CONFIG_UID_STAT=y
CONFIG_APANIC=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_UEVENT=y
CONFIG_NETDEVICES=y
CONFIG_PHYLIB=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_WLAN_80211=y
CONFIG_USB_USBNET=y
CONFIG_PPP=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_MPPE=y
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_KEYRESET=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
CONFIG_INPUT_TABLET=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_KEYCHORD=y
CONFIG_INPUT_UINPUT=y
CONFIG_SENSOR_DEVICE=y
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C0_CONTROLLER_RK30=y
CONFIG_I2C1_CONTROLLER_RK30=y
CONFIG_I2C2_CONTROLLER_RK30=y
CONFIG_I2C3_CONTROLLER_RK30=y
CONFIG_ADC_RK30=y
CONFIG_EXPANDED_GPIO_NUM=0
CONFIG_EXPANDED_GPIO_IRQ_NUM=0
CONFIG_SPI_FPGA_GPIO_NUM=0
CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
CONFIG_POWER_SUPPLY=y
CONFIG_TEST_POWER=y
# CONFIG_HWMON is not set
CONFIG_MFD_TPS65910=y
CONFIG_MFD_TPS65090=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_RK30_PWM_REGULATOR=y
CONFIG_ION=y
CONFIG_ION_ROCKCHIP=y
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_RK2928_A720=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK2928=y
CONFIG_RGA_RK30=y
CONFIG_RK_LVDS=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_BMP is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SOC=y
CONFIG_SND_RK29_SOC=y
CONFIG_SND_I2S_DMA_EVENT_STATIC=y
CONFIG_SND_RK_SOC_RK2928=y
CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=y
CONFIG_HID_ELECOM=y
CONFIG_HID_EZKEY=y
CONFIG_HID_KEYTOUCH=y
CONFIG_HID_KYE=y
CONFIG_HID_UCLOGIC=y
CONFIG_HID_WALTOP=y
CONFIG_HID_GYRATION=y
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
CONFIG_HID_LOGITECH=y
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWII_FF=y
CONFIG_HID_MAGICMOUSE=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NTRIG=y
CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
CONFIG_HID_QUANTA=y
CONFIG_HID_ROCCAT_ARVO=y
CONFIG_HID_ROCCAT_KONE=y
CONFIG_HID_ROCCAT_KONEPLUS=y
CONFIG_HID_ROCCAT_KOVAPLUS=y
CONFIG_HID_ROCCAT_PYRA=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
CONFIG_HID_SUNPLUS=y
CONFIG_HID_GREENASIA=y
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=y
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_THRUSTMASTER=y
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_WACOM=y
CONFIG_HID_ZEROPLUS=y
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_OPTION=y
CONFIG_USB_GADGET=y
CONFIG_USB20_HOST=y
CONFIG_USB20_OTG=y
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_EMBEDDED_SDIO=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_SDMMC_RK29=y
# CONFIG_SDMMC0_RK29 is not set
# CONFIG_SDMMC1_RK29 is not set
CONFIG_SWITCH=y
CONFIG_SWITCH_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_TPS65910_RTC=y
CONFIG_STAGING=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_LOGGER=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
# CONFIG_CMMB is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_EXT4_FS=y
# CONFIG_EXT4_FS_XATTR is not set
# CONFIG_DNOTIFY is not set
CONFIG_FUSE_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_EFI_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_CRYPTO_TWOFISH=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

2
arch/arm/mach-rk2928/Kconfig
View File

@@ -10,6 +10,8 @@ config MACH_RK2928_FPGA
config MACH_RK2928_SDK
bool "RK2928 SDK board"
config MACH_RK2928_A720
bool "RK2928 A720 board"
endchoice
endif

1
arch/arm/mach-rk2928/Makefile
View File

@@ -13,3 +13,4 @@ CFLAGS_pm.o += -Os -mthumb
obj-$(CONFIG_MACH_RK2928_FPGA) += board-rk2928-fpga.o
obj-$(CONFIG_MACH_RK2928_SDK) += board-rk2928-sdk.o
obj-$(CONFIG_MACH_RK2928_A720) += board-rk2928-a720.o

39
arch/arm/mach-rk2928/board-rk2928-a720-key.c Executable file
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@@ -0,0 +1,39 @@
#include <mach/gpio.h>
#include <plat/key.h>
#define EV_ENCALL KEY_F4
#define EV_MENU KEY_F1
#define PRESS_LEV_LOW 1
#define PRESS_LEV_HIGH 0
static struct rk29_keys_button key_button[] = {
{
.desc = "play",
.code = KEY_POWER,
.gpio = RK2928_PIN1_PA4,
.active_low = PRESS_LEV_LOW,
//.code_long_press = EV_ENCALL,
.wakeup = 1,
},
{
.desc = "vol+",
.code = KEY_VOLUMEUP,
.gpio = INVALID_GPIO,
.adc_value = 1,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol-",
.code = KEY_VOLUMEDOWN,
.gpio = INVALID_GPIO,
.adc_value = 512,
.active_low = PRESS_LEV_LOW,
},
};
struct rk29_keys_platform_data rk29_keys_pdata = {
.buttons = key_button,
.nbuttons = ARRAY_SIZE(key_button),
.chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
};

628
arch/arm/mach-rk2928/board-rk2928-a720-tps65910.c Executable file
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@@ -0,0 +1,628 @@
#include <linux/regulator/machine.h>
#include <linux/i2c/twl.h>
#include <linux/mfd/tps65910.h>
#include <mach/sram.h>
#include <linux/platform_device.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
#define CRU_CLKGATE5_CON_ADDR 0x00e4
#define GRF_GPIO6L_DIR_ADDR 0x0030
#define GRF_GPIO6L_DO_ADDR 0x0068
#define GRF_GPIO6L_EN_ADDR 0x00a0
#define GPIO6_PB3_DIR_OUT 0x08000800
#define GPIO6_PB3_DO_LOW 0x08000000
#define GPIO6_PB3_DO_HIGH 0x08000800
#define GPIO6_PB3_EN_MASK 0x08000800
#define GPIO6_PB3_UNEN_MASK 0x08000000
#define GPIO6_PB1_DIR_OUT 0x02000200
#define GPIO6_PB1_DO_LOW 0x02000000
#define GPIO6_PB1_DO_HIGH 0x02000200
#define GPIO6_PB1_EN_MASK 0x02000200
#define GPIO6_PB1_UNEN_MASK 0x02000000
#ifdef CONFIG_MFD_TPS65910
#define PMU_POWER_SLEEP RK2928_PIN3_PD2
extern int platform_device_register(struct platform_device *pdev);
int tps65910_pre_init(struct tps65910 *tps65910){
int val = 0;
int i = 0;
int err = -1;
printk("%s,line=%d\n", __func__,__LINE__);
gpio_request(PMU_POWER_SLEEP, "NULL");
gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
return val;
}
/* Set sleep state active high and allow device turn-off after PWRON long press */
val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
return err;
}
#if 1
/* set PSKIP=0 */
val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= ~DEVCTRL_DEV_OFF_MASK;
val &= ~DEVCTRL_DEV_SLP_MASK;
err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
return err;
}
#endif
/* Set the maxinum load current */
/* VDD1 */
val = tps65910_reg_read(tps65910, TPS65910_VDD1);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/|<7C><>s(sampling 3 Mhz/5)
err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
return err;
}
/* VDD2 */
val = tps65910_reg_read(tps65910, TPS65910_VDD2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
return err;
}
/* VIO */
val = tps65910_reg_read(tps65910, TPS65910_VIO);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
return -EIO;
}
val |= (1<<6); //when 01: 1.0 A
err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
return err;
}
#if 1
/* Mask ALL interrupts */
err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
return err;
}
err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
return err;
}
/* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
#if 1
val = 0;
val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
return err;
}
printk(KERN_INFO "TPS65910 Set default voltage.\n");
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%04x\n",__FUNCTION__,val);
}
#endif
#if 1
//sleep control register
/*set func when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= (1 << 1);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/* open ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= 0;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*set dc mode when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0xff;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*close ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0x9B;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%4x\n",__FUNCTION__,val);
}
#endif
#endif
printk("%s,line=%d\n", __func__,__LINE__);
return 0;
}
int tps65910_post_init(struct tps65910 *tps65910)
{
struct regulator *dcdc;
struct regulator *ldo;
printk("%s,line=%d\n", __func__,__LINE__);
#ifdef CONFIG_RK30_PWM_REGULATOR
platform_device_register(&pwm_regulator_device[0]);
#endif
dcdc = regulator_get(NULL, "vio"); //vcc_io
regulator_set_voltage(dcdc, 3300000, 3300000);
regulator_enable(dcdc);
printk("%s set vio vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
/*
ldo = regulator_get(NULL, "vpll"); // vcc25
regulator_set_voltage(ldo, 2500000, 2500000);
regulator_enable(ldo);
printk("%s set vpll vcc25=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
*/
ldo = regulator_get(NULL, "vdig2"); // vdd12
regulator_set_voltage(ldo, 1200000, 1200000);
regulator_enable(ldo);
printk("%s set vdig2 vdd12=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "vaux33"); //vcc_tp
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_enable(ldo);
printk("%s set vaux33 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
dcdc = regulator_get(NULL, "vdd_cpu"); //vdd_cpu
regulator_set_voltage(dcdc, 1200000, 1200000);
regulator_enable(dcdc);
printk("%s set vdd1 vdd_cpu=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
dcdc = regulator_get(NULL, "vdd2"); //vcc_ddr
regulator_set_voltage(dcdc, 1200000, 1200000); // 1.5*4/5 = 1.2 and Vout=1.5v
regulator_enable(dcdc);
printk("%s set vdd2 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "vdig1"); //vcc18_cif
regulator_set_voltage(ldo, 1500000, 1500000);
regulator_enable(ldo);
printk("%s set vdig1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
dcdc = regulator_get(NULL, "vaux1"); //vcc28_cif
regulator_set_voltage(dcdc,2800000,2800000);
regulator_enable(dcdc);
printk("%s set vaux1 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "vaux2"); //vcca33
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_enable(ldo);
printk("%s set vaux2 vcca33=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
/*
ldo = regulator_get(NULL, "vdac"); // vccio_wl
regulator_set_voltage(ldo,1800000,1800000);
regulator_enable(ldo);
printk("%s set vdac vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
*/
ldo = regulator_get(NULL, "vmmc"); //vccio_wl
regulator_set_voltage(ldo,3300000,3300000);
regulator_enable(ldo);
printk("%s set vmmc vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
printk("%s,line=%d END\n", __func__,__LINE__);
return 0;
}
static struct regulator_consumer_supply tps65910_smps1_supply[] = {
{
.supply = "vdd1",
},
{
.supply = "vdd_cpu",
},
};
static struct regulator_consumer_supply tps65910_smps2_supply[] = {
{
.supply = "vdd2",
},
};
static struct regulator_consumer_supply tps65910_smps3_supply[] = {
{
.supply = "vdd3",
},
};
static struct regulator_consumer_supply tps65910_smps4_supply[] = {
{
.supply = "vio",
},
};
static struct regulator_consumer_supply tps65910_ldo1_supply[] = {
{
.supply = "vdig1",
},
};
static struct regulator_consumer_supply tps65910_ldo2_supply[] = {
{
.supply = "vdig2",
},
};
static struct regulator_consumer_supply tps65910_ldo3_supply[] = {
{
.supply = "vaux1",
},
};
static struct regulator_consumer_supply tps65910_ldo4_supply[] = {
{
.supply = "vaux2",
},
};
static struct regulator_consumer_supply tps65910_ldo5_supply[] = {
{
.supply = "vaux33",
},
};
static struct regulator_consumer_supply tps65910_ldo6_supply[] = {
{
.supply = "vmmc",
},
};
static struct regulator_consumer_supply tps65910_ldo7_supply[] = {
{
.supply = "vdac",
},
};
static struct regulator_consumer_supply tps65910_ldo8_supply[] = {
{
.supply = "vpll",
},
};
static struct regulator_init_data tps65910_smps1 = {
.constraints = {
.name = "VDD1",
.min_uV = 600000,
.max_uV = 1500000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps1_supply),
.consumer_supplies = tps65910_smps1_supply,
};
/* */
static struct regulator_init_data tps65910_smps2 = {
.constraints = {
.name = "VDD2",
.min_uV = 600000,
.max_uV = 1500000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps2_supply),
.consumer_supplies = tps65910_smps2_supply,
};
/* */
static struct regulator_init_data tps65910_smps3 = {
.constraints = {
.name = "VDD3",
.min_uV = 1000000,
.max_uV = 1400000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps3_supply),
.consumer_supplies = tps65910_smps3_supply,
};
static struct regulator_init_data tps65910_smps4 = {
.constraints = {
.name = "VIO",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps4_supply),
.consumer_supplies = tps65910_smps4_supply,
};
static struct regulator_init_data tps65910_ldo1 = {
.constraints = {
.name = "VDIG1",
.min_uV = 1200000,
.max_uV = 2700000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo1_supply),
.consumer_supplies = tps65910_ldo1_supply,
};
/* */
static struct regulator_init_data tps65910_ldo2 = {
.constraints = {
.name = "VDIG2",
.min_uV = 1000000,
.max_uV = 1800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo2_supply),
.consumer_supplies = tps65910_ldo2_supply,
};
/* */
static struct regulator_init_data tps65910_ldo3 = {
.constraints = {
.name = "VAUX1",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo3_supply),
.consumer_supplies = tps65910_ldo3_supply,
};
/* */
static struct regulator_init_data tps65910_ldo4 = {
.constraints = {
.name = "VAUX2",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo4_supply),
.consumer_supplies = tps65910_ldo4_supply,
};
/* */
static struct regulator_init_data tps65910_ldo5 = {
.constraints = {
.name = "VAUX33",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo5_supply),
.consumer_supplies = tps65910_ldo5_supply,
};
/* */
static struct regulator_init_data tps65910_ldo6 = {
.constraints = {
.name = "VMMC",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo6_supply),
.consumer_supplies = tps65910_ldo6_supply,
};
/* */
static struct regulator_init_data tps65910_ldo7 = {
.constraints = {
.name = "VDAC",
.min_uV = 1800000,
.max_uV = 2850000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo7_supply),
.consumer_supplies = tps65910_ldo7_supply,
};
/* */
static struct regulator_init_data tps65910_ldo8 = {
.constraints = {
.name = "VPLL",
.min_uV = 1000000,
.max_uV = 2500000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo8_supply),
.consumer_supplies = tps65910_ldo8_supply,
};
/*
void __sramfunc board_pmu_tps65910_suspend(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
}
void __sramfunc board_pmu_tps65910_resume(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
#ifdef CONFIG_CLK_SWITCH_TO_32K //switch clk to 24M
sram_32k_udelay(10000);
#else
sram_udelay(2000);
#endif
}
*/
static struct tps65910_board tps65910_data = {
.irq = (unsigned)TPS65910_HOST_IRQ,
.irq_base = NR_GIC_IRQS + NR_GPIO_IRQS,
.gpio_base = TPS65910_GPIO_EXPANDER_BASE,
.pre_init = tps65910_pre_init,
.post_init = tps65910_post_init,
//TPS65910_NUM_REGS = 13
// Regulators
.tps65910_pmic_init_data[TPS65910_REG_VRTC] = NULL,
.tps65910_pmic_init_data[TPS65910_REG_VIO] = &tps65910_smps4,
.tps65910_pmic_init_data[TPS65910_REG_VDD1] = &tps65910_smps1,
.tps65910_pmic_init_data[TPS65910_REG_VDD2] = &tps65910_smps2,
.tps65910_pmic_init_data[TPS65910_REG_VDD3] = &tps65910_smps3,
.tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &tps65910_ldo1,
.tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &tps65910_ldo2,
.tps65910_pmic_init_data[TPS65910_REG_VPLL] = &tps65910_ldo8,
.tps65910_pmic_init_data[TPS65910_REG_VDAC] = &tps65910_ldo7,
.tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &tps65910_ldo3,
.tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
.tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
.tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
};
#endif

499
arch/arm/mach-rk2928/board-rk2928-a720.c Executable file
View File

@@ -0,0 +1,499 @@
/* arch/arm/mach-rk2928/board-rk2928-fpga.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/skbuff.h>
#include <linux/spi/spi.h>
#include <linux/mmc/host.h>
#include <linux/ion.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/hardware/gic.h>
#include <mach/dvfs.h>
#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/io.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <linux/fb.h>
#include <linux/regulator/machine.h>
#include <linux/rfkill-rk.h>
#include <linux/sensor-dev.h>
#include <linux/mfd/tps65910.h>
#include <linux/regulator/rk29-pwm-regulator.h>
#if defined(CONFIG_HDMI_RK30)
#include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
#endif
#if defined(CONFIG_SPIM_RK29)
#include "../../../drivers/spi/rk29_spim.h"
#endif
#include "board-rk2928-a720-key.c"
#ifdef CONFIG_THREE_FB_BUFFER
#define RK30_FB0_MEM_SIZE 12*SZ_1M
#else
#define RK30_FB0_MEM_SIZE 8*SZ_1M
#endif
static struct spi_board_info board_spi_devices[] = {
};
/***********************************************************
* rk30 backlight
************************************************************/
#ifdef CONFIG_BACKLIGHT_RK29_BL
#define PWM_ID 0
#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
#define PWM_MUX_MODE GPIO0D_PWM_0
#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
#define PWM_GPIO RK2928_PIN0_PD2
#define PWM_EFFECT_VALUE 1
#define LCD_DISP_ON_PIN
#ifdef LCD_DISP_ON_PIN
#define BL_EN_PIN RK2928_PIN1_PB0
#define BL_EN_VALUE GPIO_HIGH
#endif
static int rk29_backlight_io_init(void)
{
int ret = 0;
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
#ifdef LCD_DISP_ON_PIN
// rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
ret = gpio_request(BL_EN_PIN, NULL);
if (ret != 0) {
gpio_free(BL_EN_PIN);
}
gpio_direction_output(BL_EN_PIN, 0);
gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
#endif
return ret;
}
static int rk29_backlight_io_deinit(void)
{
int ret = 0;
#ifdef LCD_DISP_ON_PIN
gpio_free(BL_EN_PIN);
#endif
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
return ret;
}
static int rk29_backlight_pwm_suspend(void)
{
int ret = 0;
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
if (gpio_request(PWM_GPIO, NULL)) {
printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
return -1;
}
gpio_direction_output(PWM_GPIO, GPIO_LOW);
#ifdef LCD_DISP_ON_PIN
gpio_direction_output(BL_EN_PIN, 0);
gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
#endif
return ret;
}
static int rk29_backlight_pwm_resume(void)
{
gpio_free(PWM_GPIO);
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
#ifdef LCD_DISP_ON_PIN
msleep(30);
gpio_direction_output(BL_EN_PIN, 1);
gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
#endif
return 0;
}
static struct rk29_bl_info rk29_bl_info = {
.pwm_id = PWM_ID,
.bl_ref = PWM_EFFECT_VALUE,
.io_init = rk29_backlight_io_init,
.io_deinit = rk29_backlight_io_deinit,
.pwm_suspend = rk29_backlight_pwm_suspend,
.pwm_resume = rk29_backlight_pwm_resume,
};
static struct platform_device rk29_device_backlight = {
.name = "rk29_backlight",
.id = -1,
.dev = {
.platform_data = &rk29_bl_info,
}
};
#endif
#ifdef CONFIG_FB_ROCKCHIP
#define LCD_MUX_NAME GPIO0C2_UART0_RTSN_NAME
#define LCD_GPIO_MODE GPIO0C_GPIO0C2
#define LCD_EN RK2928_PIN0_PC2
#define LCD_EN_VALUE GPIO_LOW
static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
{
int ret = 0;
rk30_mux_api_set(LCD_MUX_NAME, LCD_GPIO_MODE);
ret = gpio_request(LCD_EN, NULL);
if (ret != 0)
{
gpio_free(LCD_EN);
printk(KERN_ERR "request lcd en pin fail!\n");
return -1;
}
else
{
gpio_direction_output(LCD_EN, LCD_EN_VALUE); //disable
}
return 0;
}
static int rk_fb_io_disable(void)
{
gpio_set_value(LCD_EN, !LCD_EN_VALUE);
return 0;
}
static int rk_fb_io_enable(void)
{
gpio_set_value(LCD_EN, LCD_EN_VALUE);
return 0;
}
#if defined(CONFIG_LCDC_RK2928)
struct rk29fb_info lcdc_screen_info = {
.prop = PRMRY, //primary display device
.io_init = rk_fb_io_init,
.io_disable = rk_fb_io_disable,
.io_enable = rk_fb_io_enable,
.set_screen_info = set_lcd_info,
};
#endif
static struct resource resource_fb[] = {
[0] = {
.name = "fb0 buf",
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "ipp buf", //for rotate
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.name = "fb2 buf",
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_fb = {
.name = "rk-fb",
.id = -1,
.num_resources = ARRAY_SIZE(resource_fb),
.resource = resource_fb,
};
#endif
#ifdef CONFIG_ION
#define ION_RESERVE_SIZE (80 * SZ_1M)
static struct ion_platform_data rk30_ion_pdata = {
.nr = 1,
.heaps = {
{
.type = ION_HEAP_TYPE_CARVEOUT,
.id = ION_NOR_HEAP_ID,
.name = "norheap",
.size = ION_RESERVE_SIZE,
}
},
};
static struct platform_device device_ion = {
.name = "ion-rockchip",
.id = 0,
.dev = {
.platform_data = &rk30_ion_pdata,
},
};
#endif
#if CONFIG_RK30_PWM_REGULATOR
const static int pwm_voltage_map[] = {
1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
};
static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
{
.supply = "vdd_core",
}
};
struct regulator_init_data pwm_regulator_init_dcdc[1] =
{
{
.constraints = {
.name = "PWM_DCDC1",
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
.consumer_supplies = pwm_dcdc1_consumers,
},
};
static struct pwm_platform_data pwm_regulator_info[1] = {
{
.pwm_id = 2,
.pwm_gpio = RK2928_PIN0_PD4,
.pwm_iomux_name = GPIO0D4_PWM_2_NAME,
.pwm_iomux_pwm = GPIO0D_PWM_2,
.pwm_iomux_gpio = GPIO0D_GPIO0D4,
.pwm_voltage = 1200000,
.suspend_voltage = 1050000,
.min_uV = 1000000,
.max_uV = 1400000,
.coefficient = 455, //45.5%
.pwm_voltage_map = pwm_voltage_map,
.init_data = &pwm_regulator_init_dcdc[0],
},
};
struct platform_device pwm_regulator_device[1] = {
{
.name = "pwm-voltage-regulator",
.id = 0,
.dev = {
.platform_data = &pwm_regulator_info[0],
}
},
};
#endif
static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_BACKLIGHT_RK29_BL
&rk29_device_backlight,
#endif
#ifdef CONFIG_FB_ROCKCHIP
&device_fb,
#endif
#ifdef CONFIG_ION
&device_ion,
#endif
};
//i2c
#ifdef CONFIG_I2C0_RK30
#ifdef CONFIG_MFD_TPS65910
#define TPS65910_HOST_IRQ RK2928_PIN1_PB2
#include "board-rk2928-a720-tps65910.c"
#endif
static struct i2c_board_info __initdata i2c0_info[] = {
#if defined (CONFIG_MFD_TPS65910)
{
.type = "tps65910",
.addr = TPS65910_I2C_ID0,
.flags = 0,
.irq = TPS65910_HOST_IRQ,
.platform_data = &tps65910_data,
},
#endif
};
#endif
#ifdef CONFIG_I2C1_RK30
static struct i2c_board_info __initdata i2c1_info[] = {
};
#endif
#ifdef CONFIG_I2C2_RK30
static struct i2c_board_info __initdata i2c2_info[] = {
};
#endif
#ifdef CONFIG_I2C3_RK30
static struct i2c_board_info __initdata i2c3_info[] = {
};
#endif
#ifdef CONFIG_I2C_GPIO_RK30
#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
static int rk30_i2c_io_init(void)
{
//set iomux (gpio) here
return 0;
}
struct i2c_gpio_platform_data default_i2c_gpio_data = {
.sda_pin = I2C_SDA_PIN,
.scl_pin = I2C_SCL_PIN,
.udelay = 5, // clk = 500/udelay = 100Khz
.timeout = 100,//msecs_to_jiffies(100),
.bus_num = 5,
.io_init = rk30_i2c_io_init,
};
static struct i2c_board_info __initdata i2c_gpio_info[] = {
};
#endif
static void __init rk30_i2c_register_board_info(void)
{
#ifdef CONFIG_I2C0_RK30
i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
#endif
#ifdef CONFIG_I2C1_RK30
i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
#endif
#ifdef CONFIG_I2C2_RK30
i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
#endif
#ifdef CONFIG_I2C3_RK30
i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
#endif
#ifdef CONFIG_I2C_GPIO_RK30
i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
#endif
}
//end of i2c
#define POWER_ON_PIN RK2928_PIN1_PA4 //power_hold
static void rk2928_pm_power_off(void)
{
printk(KERN_ERR "rk2928_pm_power_off start...\n");
#if defined(CONFIG_MFD_TPS65910)
tps65910_device_shutdown();//tps65910 shutdown
#endif
gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
};
static void __init rk2928_board_init(void)
{
gpio_request(POWER_ON_PIN, "poweronpin");
gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
gpio_free(POWER_ON_PIN);
pm_power_off = rk2928_pm_power_off;
rk30_i2c_register_board_info();
spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init rk2928_reserve(void)
{
#ifdef CONFIG_ION
rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
#endif
#ifdef CONFIG_FB_ROCKCHIP
resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
#endif
#ifdef CONFIG_VIDEO_RK29
rk30_camera_request_reserve_mem();
#endif
board_mem_reserved();
}
/**
* dvfs_cpu_logic_table: table for arm and logic dvfs
* @frequency : arm frequency
* @cpu_volt : arm voltage depend on frequency
* @logic_volt : logic voltage arm requests depend on frequency
* comments : min arm/logic voltage
*/
static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
{.frequency = 216 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//0.975V/1.000V
{.frequency = 312 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//0.975V/1.000V
{.frequency = 408 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//1.000V/1.025V
{.frequency = 504 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//1.000V/1.025V
{.frequency = 600 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//1.025V/1.050V
//{.frequency = 696 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.000V/1.025V
//{.frequency = 816 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
//{.frequency = 912 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
#if 0
{.frequency = 1008 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
#endif
//{.frequency = 1000 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},//1.150V/1.100V
{.frequency = CPUFREQ_TABLE_END},
};
static struct cpufreq_frequency_table dvfs_gpu_table[] = {
{.frequency = 266 * 1000, .index = 1050 * 1000},
{.frequency = 400 * 1000, .index = 1275 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
static struct cpufreq_frequency_table dvfs_ddr_table[] = {
{.frequency = 300 * 1000, .index = 1050 * 1000},
{.frequency = 400 * 1000, .index = 1125 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
void __init board_clock_init(void)
{
rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
//dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
printk("%s end\n", __func__);
}
MACHINE_START(RK2928, "RK2928board")
.boot_params = PLAT_PHYS_OFFSET + 0x800,
.fixup = rk2928_fixup,
.reserve = &rk2928_reserve,
.map_io = rk2928_map_io,
.init_irq = rk2928_init_irq,
.timer = &rk2928_timer,
.init_machine = rk2928_board_init,
MACHINE_END

2
arch/arm/mach-rk2928/clock_data.c
View File

@@ -2449,7 +2449,7 @@ static void __init rk2928_clock_common_init(unsigned long gpll_rate,unsigned lon
{
CLKDATA_DBG("ENTER %s\n", __func__);
clk_set_rate_nolock(&clk_core_pre, 816 * MHZ);//816
clk_set_rate_nolock(&clk_core_pre, 600 * MHZ);//816?
//general
clk_set_rate_nolock(&general_pll_clk, gpll_rate);
//code pll

2
drivers/input/keyboard/rk29_keys.c
View File

@@ -29,7 +29,7 @@
#define EMPTY_ADVALUE 950
#define DRIFT_ADVALUE 70
#define INVALID_ADVALUE 10
#define INVALID_ADVALUE -1
#define EV_MENU KEY_F1

3
drivers/video/display/screen/Kconfig
View File

@@ -92,6 +92,9 @@ config LCD_HV070WSA100
bool "HV070WSA-100 1024X600"
config LCD_COMMON
bool "LCD COMMON"
config LCD_RK2928_A720
bool "RK2928 A720 panel 800x480"
endchoice

1
drivers/video/display/screen/Makefile
View File

@@ -42,3 +42,4 @@ obj-$(CONFIG_LCD_HJ050NA_06A) += lcd_hj050na_06a.o
obj-$(CONFIG_LCD_HSD100PXN_FOR_TDW851) += lcd_hsd100pxn_for_tdw851.o
obj-$(CONFIG_LCD_HV070WSA100) += lcd_hv070wsa.o
obj-$(CONFIG_LCD_COMMON) += lcd_common.o
obj-$(CONFIG_LCD_RK2928_A720) += lcd_rk2928_a720.o

80
drivers/video/display/screen/lcd_rk2928_a720.c Normal file
View File

@@ -0,0 +1,80 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P666
#define OUT_CLK 30000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 48 //10
#define H_BP 40 //100
#define H_VD 800 //1024
#define H_FP 40 //210
#define V_PW 3 //10
#define V_BP 29 //10
#define V_VD 480 //768
#define V_FP 13 //18
/* Other */
#define DCLK_POL 0
#define SWAP_RB 0
#define LCD_WIDTH 154 //need modify
#define LCD_HEIGHT 85
static struct rk29lcd_info *gLcd_info = NULL;
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
/*screen->init = init;*/
screen->init = NULL;
screen->standby = NULL;
if(lcd_info)
gLcd_info = lcd_info;
}

25
drivers/video/rockchip/chips/rk2928_lcdc.c
View File

@@ -30,6 +30,7 @@
#include <linux/earlysuspend.h>
#include <asm/div64.h>
#include <asm/uaccess.h>
#include <mach/iomux.h>
#include "rk2928_lcdc.h"
#include "../lvds/rk_lvds.h"
@@ -71,6 +72,30 @@ static int init_rk2928_lcdc(struct rk_lcdc_device_driver *dev_drv)
#ifdef CONFIG_RK_LVDS
rk_lvds_register(lcdc_dev->screen);
#endif
if(lcdc_dev->screen->type == SCREEN_RGB) //iomux for RGB screen
{
rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_LCDC0_DCLK);
rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B_LCDC0_HSYNC);
rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_LCDC0_VSYNC);
rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_LCDC0_DEN);
rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_LCDC0_D10);
rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_LCDC0_D11);
rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_LCDC0_D12);
rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_LCDC0_D13);
rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_LCDC0_D14);
rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_LCDC0_D15);
rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_LCDC0_D16);
rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_LCDC0_D17);
//rk30_mux_api_set(GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME, GPIO2C_LCDC1_D18);
//rk30_mux_api_set(GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME, GPIO2C_LCDC1_D19);
//rk30_mux_api_set(GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME, GPIO2C_LCDC1_D20);
//rk30_mux_api_set(GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME, GPIO2C_LCDC1_D21);
//rk30_mux_api_set(GPIO2D0_LCDC0_D22_LCDC1_D22_NAME, GPIO2D_LCDC1_D22);
//rk30_mux_api_set(GPIO2D1_LCDC0_D23_LCDC1_D23_NAME, GPIO2D_LCDC1_D23);
printk("RGB screen connect to rk2928\n");
}
clk_enable(lcdc_dev->pd);
clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config