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Revert "ARM: Cortex-A9: Enable dynamic clock gating"

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This reverts commit 91406b03fa.
This commit is contained in:
Rebecca Schultz Zavin
2011-03-22 11:04:55 -07:00
parent a0b2620b8e
commit ed6cbef145
2 changed files with 0 additions and 20 deletions
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10
arch/arm/Kconfig
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@@ -1115,16 +1115,6 @@ config ARM_ERRATA_743622
visible impact on the overall performance or power consumption of the
processor.
config ARM_ERRATA_720791
bool "ARM errata: Dynamic high-level clock gating corrupts the Jazelle instruction stream"
depends on CPU_V7
help
This option enables the workaround for the 720791 Cortex-A9
(r1p0..r1p2) erratum. The Jazelle instruction stream may be
corrupted when dynamic high-level clock gating is enabled.
This workaround disables gating the Core clock when the Instruction
side is waiting for a Page Table Walk answer or linefill completion.
endmenu
source "arch/arm/common/Kconfig"

10
arch/arm/mm/proc-v7.S
View File

@@ -238,16 +238,6 @@ __v7_setup:
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
cmp r6, #0x10 @ power ctrl reg added r1p0
mrcge p15, 0, r10, c15, c0, 0 @ read power control register
orrge r10, r10, #1 @ enable dynamic clock gating
mcrge p15, 0, r10, c15, c0, 0 @ write power control register
#ifdef CONFIG_ARM_ERRATA_720791
teq r5, #0x00100000 @ only present in r1p*
mrceq p15, 0, r10, c15, c0, 2 @ read "chicken power ctrl" reg
orreq r10, r10, #0x30 @ disable core clk gate on
mcreq p15, 0, r10, c15, c0, 2 @ instr-side waits
#endif
#ifdef CONFIG_ARM_ERRATA_742230
cmp r6, #0x22 @ only present up to r2p2
mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register