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Revert "ANDROID: arm64: kvm: Hide asym aarch32 systems from KVM"
This reverts commit b674244dc1.
Bug: 178507149
Signed-off-by: Will Deacon <willdeacon@google.com>
Change-Id: Ia0cdd883546c1ffa0f517910d09c6730ff7b2006
This commit is contained in:
@@ -614,15 +614,6 @@ static inline bool system_supports_32bit_el0(void)
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return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);
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}
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static inline bool kvm_system_supports_32bit_el0(void)
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{
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#ifndef CONFIG_ASYMMETRIC_AARCH32
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return system_supports_32bit_el0();
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#else
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return cpumask_equal(&aarch32_el0_mask, cpu_possible_mask);
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#endif
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}
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static inline bool system_supports_4kb_granule(void)
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{
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u64 mmfr0;
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@@ -225,7 +225,7 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
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u64 mode = (*(u64 *)valp) & PSR_AA32_MODE_MASK;
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switch (mode) {
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case PSR_AA32_MODE_USR:
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if (!kvm_system_supports_32bit_el0())
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if (!system_supports_32bit_el0())
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return -EINVAL;
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break;
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case PSR_AA32_MODE_FIQ:
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@@ -617,7 +617,7 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
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*/
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val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
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| (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
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if (!kvm_system_supports_32bit_el0())
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if (!system_supports_32bit_el0())
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val |= ARMV8_PMU_PMCR_LC;
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__vcpu_sys_reg(vcpu, r->reg) = val;
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}
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@@ -666,7 +666,7 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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val = __vcpu_sys_reg(vcpu, PMCR_EL0);
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val &= ~ARMV8_PMU_PMCR_MASK;
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val |= p->regval & ARMV8_PMU_PMCR_MASK;
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if (!kvm_system_supports_32bit_el0())
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if (!system_supports_32bit_el0())
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val |= ARMV8_PMU_PMCR_LC;
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__vcpu_sys_reg(vcpu, PMCR_EL0) = val;
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kvm_pmu_handle_pmcr(vcpu, val);
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@@ -1036,15 +1036,6 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
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val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT);
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val &= ~(0xfUL << ID_AA64PFR0_CSV3_SHIFT);
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val |= ((u64)vcpu->kvm->arch.pfr0_csv3 << ID_AA64PFR0_CSV3_SHIFT);
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if (!kvm_system_supports_32bit_el0()) {
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/*
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* We could be running on asym aarch32 system.
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* Override to present a aarch64 only system.
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*/
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val &= ~(0xfUL << ID_AA64PFR0_EL0_SHIFT);
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val |= (ID_AA64PFR0_EL0_64BIT_ONLY << ID_AA64PFR0_EL0_SHIFT);
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}
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} else if (id == SYS_ID_AA64PFR1_EL1) {
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val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
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} else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
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