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osd: fix osd color error when osd hdr enabled [1/1]

Browse Source 
PD#SWPL-1804

Problem:
osd color error when osd hdr enabled

Solution:
div alpha when osd hdr enabled

Verify:
verified on u212 dev board

Change-Id: I1f5ea0db404d1956f454bd5da2532bded89626ee
Signed-off-by: pengcheng chen <pengcheng.chen@amlogic.com>
This commit is contained in:
pengcheng chen
2018-11-22 12:54:06 +08:00
committed by Jianxin Pan
parent efc2d96311
commit eda95208fc
2 changed files with 19 additions and 2 deletions
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6
drivers/amlogic/media/osd/osd_debug.c
View File

@@ -196,10 +196,16 @@ static void osd_debug_dump_register_all(void)
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
reg = VPP_OSD2_BLD_V_SCOPE;
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
reg = VD1_BLEND_SRC_CTRL;
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
reg = VD2_BLEND_SRC_CTRL;
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
reg = OSD1_BLEND_SRC_CTRL;
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
reg = OSD2_BLEND_SRC_CTRL;
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
reg = VIU_OSD_BLEND_CTRL1;
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
reg = VPP_POSTBLEND_H_SIZE;
osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
reg = VPP_OUT_H_V_SIZE;

15
drivers/amlogic/media/osd/osd_hw.c
View File

@@ -7157,6 +7157,7 @@ static void set_blend_reg(struct layer_blend_reg_s *blend_reg)
{
int i;
u32 reg_offset = 2;
u32 osd1_alpha_div = 0, osd2_alpha_div = 0;
#ifdef OSD_BLEND_SHIFT_WORKAROUND
u32 osd_count = OSD_BLEND_LAYERS;
#else
@@ -7175,19 +7176,29 @@ static void set_blend_reg(struct layer_blend_reg_s *blend_reg)
blend_reg->blend_din_en << 20|
blend_reg->din_premult_en << 16|
blend_reg->din_reoder_sel);
if (blend_reg->postbld_osd1_premult)
osd1_alpha_div = 1;
if (blend_reg->postbld_osd2_premult)
osd2_alpha_div = 1;
/* VIU_OSD_BLEND_CTRL1 */
VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_CTRL1,
(osd1_alpha_div & 0x1) |
(3 << 4) |
((osd2_alpha_div & 0x1) << 12) |
(3 << 16));
/* vpp osd1 blend ctrl */
VSYNCOSD_WR_MPEG_REG(OSD1_BLEND_SRC_CTRL,
(0 & 0xf) << 0 |
(0 & 0x1) << 4 |
(blend_reg->postbld_src3_sel & 0xf) << 8 |
(blend_reg->postbld_osd1_premult & 0x1) << 16|
(0 << 16) |
(1 & 0x1) << 20);
/* vpp osd2 blend ctrl */
VSYNCOSD_WR_MPEG_REG(OSD2_BLEND_SRC_CTRL,
(0 & 0xf) << 0 |
(0 & 0x1) << 4 |
(blend_reg->postbld_src4_sel & 0xf) << 8 |
(blend_reg->postbld_osd2_premult & 0x1) << 16 |
(0 << 16) |
(1 & 0x1) << 20);
VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_BLEND0_SIZE,