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pinctrl: rockchip: add rk3528 support

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Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536
This commit is contained in:
Steven Liu
2022-08-11 15:15:28 +08:00
committed by Tao Huang
parent 7eb478dd39
commit ee5af82a6f
2 changed files with 196 additions and 1 deletions
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196
drivers/pinctrl/pinctrl-rockchip.c
View File

@@ -2271,6 +2271,150 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RK3528_DRV_BITS_PER_PIN 8
#define RK3528_DRV_PINS_PER_REG 2
#define RK3528_DRV_GPIO0_OFFSET 0x100
#define RK3528_DRV_GPIO1_OFFSET 0x20120
#define RK3528_DRV_GPIO2_OFFSET 0x30160
#define RK3528_DRV_GPIO3_OFFSET 0x20190
#define RK3528_DRV_GPIO4_OFFSET 0x101C0
static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
switch (bank->bank_num) {
case 0:
*reg = RK3528_DRV_GPIO0_OFFSET;
break;
case 1:
*reg = RK3528_DRV_GPIO1_OFFSET;
break;
case 2:
*reg = RK3528_DRV_GPIO2_OFFSET;
break;
case 3:
*reg = RK3528_DRV_GPIO3_OFFSET;
break;
case 4:
*reg = RK3528_DRV_GPIO4_OFFSET;
break;
default:
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
break;
}
*reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RK3528_DRV_PINS_PER_REG;
*bit *= RK3528_DRV_BITS_PER_PIN;
return 0;
}
#define RK3528_PULL_BITS_PER_PIN 2
#define RK3528_PULL_PINS_PER_REG 8
#define RK3528_PULL_GPIO0_OFFSET 0x200
#define RK3528_PULL_GPIO1_OFFSET 0x20210
#define RK3528_PULL_GPIO2_OFFSET 0x30220
#define RK3528_PULL_GPIO3_OFFSET 0x20230
#define RK3528_PULL_GPIO4_OFFSET 0x10240
static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
switch (bank->bank_num) {
case 0:
*reg = RK3528_PULL_GPIO0_OFFSET;
break;
case 1:
*reg = RK3528_PULL_GPIO1_OFFSET;
break;
case 2:
*reg = RK3528_PULL_GPIO2_OFFSET;
break;
case 3:
*reg = RK3528_PULL_GPIO3_OFFSET;
break;
case 4:
*reg = RK3528_PULL_GPIO4_OFFSET;
break;
default:
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
break;
}
*reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3528_PULL_PINS_PER_REG;
*bit *= RK3528_PULL_BITS_PER_PIN;
return 0;
}
#define RK3528_SMT_BITS_PER_PIN 1
#define RK3528_SMT_PINS_PER_REG 8
#define RK3528_SMT_GPIO0_OFFSET 0x400
#define RK3528_SMT_GPIO1_OFFSET 0x20410
#define RK3528_SMT_GPIO2_OFFSET 0x30420
#define RK3528_SMT_GPIO3_OFFSET 0x20430
#define RK3528_SMT_GPIO4_OFFSET 0x10440
static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
switch (bank->bank_num) {
case 0:
*reg = RK3528_SMT_GPIO0_OFFSET;
break;
case 1:
*reg = RK3528_SMT_GPIO1_OFFSET;
break;
case 2:
*reg = RK3528_SMT_GPIO2_OFFSET;
break;
case 3:
*reg = RK3528_SMT_GPIO3_OFFSET;
break;
case 4:
*reg = RK3528_SMT_GPIO4_OFFSET;
break;
default:
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
break;
}
*reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
*bit = pin_num % RK3528_SMT_PINS_PER_REG;
*bit *= RK3528_SMT_BITS_PER_PIN;
return 0;
}
#define RK3568_SR_PMU_OFFSET 0x60
#define RK3568_SR_GRF_OFFSET 0x0180
#define RK3568_SR_BANK_STRIDE 0x10
@@ -2686,7 +2830,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
rmask_bits = RV1126_DRV_BITS_PER_PIN;
ret = strength;
goto config;
} else if (ctrl->type == RV1106 || ctrl->type == RK3568) {
} else if (ctrl->type == RV1106 || ctrl->type == RK3568 || ctrl->type == RK3528) {
rmask_bits = RK3568_DRV_BITS_PER_PIN;
ret = (1 << (strength + 1)) - 1;
goto config;
@@ -2858,6 +3002,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
case RK3308:
case RK3368:
case RK3399:
case RK3528:
case RK3568:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
@@ -2910,6 +3055,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3308:
case RK3368:
case RK3399:
case RK3528:
case RK3568:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
@@ -3244,6 +3390,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RK3308:
case RK3368:
case RK3399:
case RK3528:
case RK3568:
case RK3588:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
@@ -4532,6 +4679,49 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl __maybe_unused = {
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk3528_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x20020, 0x20028, 0x20030, 0x20038),
PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x30040, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x20060, 0x20068, 0x20070, 0),
PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x10080, 0x10088, 0x10090, 0x10098),
};
static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = {
.pin_banks = rk3528_pin_banks,
.nr_banks = ARRAY_SIZE(rk3528_pin_banks),
.label = "RK3528-GPIO",
.type = RK3528,
.pull_calc_reg = rk3528_calc_pull_reg_and_bit,
.drv_calc_reg = rk3528_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk3568_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
@@ -4662,6 +4852,10 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rk3399-pinctrl",
.data = &rk3399_pin_ctrl },
#endif
#ifdef CONFIG_CPU_RK3528
{ .compatible = "rockchip,rk3528-pinctrl",
.data = &rk3528_pin_ctrl },
#endif
#ifdef CONFIG_CPU_RK3568
{ .compatible = "rockchip,rk3568-pinctrl",
.data = &rk3568_pin_ctrl },

1
drivers/pinctrl/pinctrl-rockchip.h
View File

@@ -199,6 +199,7 @@ enum rockchip_pinctrl_type {
RK3308,
RK3368,
RK3399,
RK3528,
RK3568,
RK3588,
};