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arm64: dts: rockchip: change default camera to imx327 on rk3399pro linux
Change-Id: Id2f375cab92ac23d81a820c8269fef0c98cb3bc4 Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
This commit is contained in:
@@ -726,6 +726,29 @@
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};
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};
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};
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imx327: imx327@1a {
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compatible = "sony,imx327";
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status = "okay";
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reg = <0x1a>;
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clocks = <&cru SCLK_CIF_OUT>;
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clock-names = "xvclk";
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/* conflict with csi-ctl-gpios */
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reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cif_clkout>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "TongJu";
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rockchip,camera-module-lens-name = "CHT842-MD";
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port {
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ucam_out2: endpoint {
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remote-endpoint = <&mipi_in_ucam2>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&i2c4 {
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@@ -836,6 +859,12 @@
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remote-endpoint = <&ucam_out0>;
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data-lanes = <1 2>;
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};
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mipi_in_ucam2: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&ucam_out2>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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@@ -874,6 +903,8 @@
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&rkisp1_0 {
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status = "okay";
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assigned-clocks = <&cru PLL_NPLL>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_CIF_OUT>;
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assigned-clock-rates = <594000000>, <594000000>, <37125000>;
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port {
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#address-cells = <1>;
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@@ -736,6 +736,30 @@
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};
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};
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};
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imx327: imx327@1a {
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compatible = "sony,imx327";
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status = "okay";
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reg = <0x1a>;
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clocks = <&cru SCLK_CIF_OUT>;
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clock-names = "xvclk";
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/* conflict with csi-ctl-gpios */
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reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cif_clkout>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "TongJu";
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rockchip,camera-module-lens-name = "CHT842-MD";
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port {
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ucam_out2: endpoint {
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remote-endpoint = <&mipi_in_ucam2>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&i2c4 {
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@@ -847,6 +871,12 @@
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remote-endpoint = <&ucam_out0>;
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data-lanes = <1 2>;
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};
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mipi_in_ucam2: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&ucam_out2>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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@@ -885,6 +915,8 @@
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&rkisp1_0 {
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status = "okay";
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assigned-clocks = <&cru PLL_NPLL>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_CIF_OUT>;
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assigned-clock-rates = <594000000>, <594000000>, <37125000>;
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port {
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#address-cells = <1>;
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