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clk: rockchip: rk3308: Change apll to boost pll

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Change-Id: I34d445e65181e09a3069b48059ef7283f01c194f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-05-09 16:54:43 +08:00
committed by Tao Huang
parent 2e21f345c3
commit ee63aafed5
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/rockchip/clk-rk3308.c
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@@ -129,6 +129,7 @@ static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
.mux_core_main = 0,
.mux_core_shift = 6,
.mux_core_mask = 0x3,
.pll_name = "pll_apll",
};
PNAME(mux_pll_p) = { "xin24m" };
@@ -189,7 +190,7 @@ PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
[apll] = PLL_BOOST(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0, RK3308_PLL_CON(0),
RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates),
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,