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clk: rockchip: rk3568: fix pwm clk register description

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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I30a8c97c95be15ea23a485e9e429fd575605b38a
This commit is contained in:
Elaine Zhang
2023-06-16 09:12:49 +08:00
committed by Tao Huang
parent ed36cde37c
commit eebe228530
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/rockchip/clk-rk3568.c
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@@ -1387,21 +1387,21 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
RK3568_CLKSEL_CON(72), 8, 2, MFLAGS,
RK3568_CLKGATE_CON(31), 11, GFLAGS),
GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
RK3568_CLKGATE_CON(31), 12, GFLAGS),
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0,
RK3568_CLKGATE_CON(31), 13, GFLAGS),
COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
RK3568_CLKSEL_CON(72), 10, 2, MFLAGS,
RK3568_CLKGATE_CON(31), 14, GFLAGS),
GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
RK3568_CLKGATE_CON(31), 15, GFLAGS),
GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0,
RK3568_CLKGATE_CON(32), 0, GFLAGS),
COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
RK3568_CLKSEL_CON(72), 12, 2, MFLAGS,
RK3568_CLKGATE_CON(32), 1, GFLAGS),
GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
RK3568_CLKGATE_CON(32), 2, GFLAGS),