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deinterlace: avoid timeout when enable iotrace [1/1]

Browse Source 
PD#SWPL-19670

Problem:
when enalbe io trace, di will timeout

Solution:
switch seting order about mif enable and reset

Verify:
u212

Change-Id: Ie2e2b6a120d43a554458d655bbb475988c4e9028
Signed-off-by: qianqian.cai <qianqian.cai@amlogic.com>
This commit is contained in:
qianqian.cai
2020-01-09 11:04:04 +08:00
committed by Chris KIM
parent 5f20bae263
commit eef1277a7f
3 changed files with 34 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/amlogic/media/deinterlace/deinterlace.c
View File

@@ -3639,14 +3639,16 @@ static void pre_de_process(void)
* otherwise may cause watch dog reboot
*/
di_lock_irqfiq_save(irq_flag2);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
/* enable mc pre mif*/
enable_di_pre_mif(true, mcpre_en);
pre_frame_reset_g12(di_pre_stru.madi_enable,
di_pre_stru.mcdi_enable);
else
} else {
pre_frame_reset();
/* enable mc pre mif*/
enable_di_pre_mif(true, mcpre_en);
/* enable mc pre mif*/
enable_di_pre_mif(true, mcpre_en);
}
di_unlock_irqfiq_restore(irq_flag2);
/*reinit pre busy flag*/
di_pre_stru.pre_de_busy_timer_count = 0;
@@ -5135,8 +5137,10 @@ static irqreturn_t de_irq(int irq, void *dev_instance)
DI_Wr(DI_INTR_CTRL, data32);
}
#else
if (flag)
if (flag) {
di_hpre_gl_sw(false);
DI_Wr(DI_INTR_CTRL, (data32&0xfffffffb)|(intr_mode<<30));
}
#endif
if (di_pre_stru.pre_de_busy == 0) {
@@ -6982,9 +6986,10 @@ static void di_pre_size_change(unsigned short width,
}
di_load_pq_table();
#ifdef OLD_PRE_GL
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
RDMA_WR(DI_PRE_GL_CTRL, 0x80000005);
#endif
if (de_devp->nrds_enable)
nr_ds_init(width, height);
if (de_devp->pps_enable && pps_position) {

21
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

@@ -435,7 +435,11 @@ static void pre_hold_block_mode_config(void)
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
DI_Wr(DI_PRE_HOLD, 0);
/* go field after 2 lines */
#ifdef OLD_PRE_GL
DI_Wr(DI_PRE_GL_CTRL, (0x80000000|line_num_pre_frst));
#else
di_hpre_gl_sw(false);
#endif
} else if (is_meson_txlx_cpu()) {
/* setup pre process ratio to 66.6%*/
DI_Wr(DI_PRE_HOLD, (1 << 31) | (1 << 16) | 3);
@@ -3232,11 +3236,28 @@ void pre_frame_reset_g12(unsigned char madi_en,
RDMA_WR_BITS(MCVECWR_CAN_SIZE, 0, 14, 1);
RDMA_WR_BITS(MCINFWR_CAN_SIZE, 0, 14, 1);
#ifdef OLD_PRE_GL
reg_val = 0xc3200000 | line_num_pre_frst;
RDMA_WR(DI_PRE_GL_CTRL, reg_val);
reg_val = 0x83200000 | line_num_pre_frst;
RDMA_WR(DI_PRE_GL_CTRL, reg_val);
#else
di_hpre_gl_sw(true);
#endif
}
/*2019-12-25 by feijun*/
void di_hpre_gl_sw(bool on)
{
if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
return;
if (on)
RDMA_WR(DI_PRE_GL_CTRL,
0x80200000 | line_num_pre_frst);
else
RDMA_WR(DI_PRE_GL_CTRL, 0xc0000000);
}
/*
* frame + soft reset for the pre modules
*/

1
drivers/amlogic/media/deinterlace/deinterlace_hw.h
View File

@@ -202,6 +202,7 @@ void pulldown_vof_win_config(struct pulldown_detected_s *wins);
void di_load_regs(struct di_pq_parm_s *di_pq_ptr);
void pre_frame_reset_g12(unsigned char madi_en, unsigned char mcdi_en);
void pre_frame_reset(void);
void di_hpre_gl_sw(bool on);
void di_interrupt_ctrl(unsigned char ma_en,
unsigned char det3d_en, unsigned char nrds_en,
unsigned char post_wr, unsigned char mc_en);