shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: add cpu dvfs support for rk3368

Browse Source 
we only add the property of regulator and clock to cpu0 and cpu4 node,
but if cpu4~cpu7 is down and then we up cpu5~cpu7, they will can not
get their regulator and clock. So we should add the properties to all
cpu node.

Change-Id: Id601fa3d3d05875f7c68f2a5472dc0eefefb6096
Signed-off-by: Feng Xiao <xf@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Xiao Feng
2016-01-12 10:44:35 +08:00
committed by Tao Huang
parent 312163c755
commit ef77f8d634
1 changed files with 162 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

162
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@@ -77,6 +77,8 @@
reg = <0x0 0x0>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_l1: cpu@1 {
@@ -85,6 +87,8 @@
reg = <0x0 0x1>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_l2: cpu@2 {
@@ -93,6 +97,8 @@
reg = <0x0 0x2>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_l3: cpu@3 {
@@ -101,6 +107,8 @@
reg = <0x0 0x3>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_b0: cpu@100 {
@@ -109,6 +117,8 @@
reg = <0x0 0x100>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
cpu_b1: cpu@101 {
@@ -117,6 +127,8 @@
reg = <0x0 0x101>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
cpu_b2: cpu@102 {
@@ -125,6 +137,8 @@
reg = <0x0 0x102>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
cpu_b3: cpu@103 {
@@ -133,6 +147,154 @@
reg = <0x0 0x103>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
rockchip,leakage-voltage-sel = <
1 24 0
25 254 1
>;
nvmem-cells = <&cpu_leakage>;
nvmem-cell-names = "cpu_leakage";
opp-216000000 {
opp-hz = /bits/ 64 <216000000>;
opp-microvolt = <950000 950000 1350000>;
opp-microvolt-L0 = <1050000 1050000 1350000>;
opp-microvolt-L1 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000 950000 1350000>;
opp-microvolt-L0 = <1050000 1050000 1350000>;
opp-microvolt-L1 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000 950000 1350000>;
opp-microvolt-L0 = <1050000 1050000 1350000>;
opp-microvolt-L1 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1025000 1025000 1350000>;
opp-microvolt-L0 = <1125000 1125000 1350000>;
opp-microvolt-L1 = <1025000 1025000 1350000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1125000 1125000 1350000>;
opp-microvolt-L0 = <1225000 1225000 1350000>;
opp-microvolt-L1 = <1125000 1125000 1350000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1225000 1225000 1350000>;
opp-microvolt-L0 = <1325000 1325000 1350000>;
opp-microvolt-L1 = <1225000 1225000 1350000>;
clock-latency-ns = <40000>;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
rockchip,leakage-scaling-sel = <
1 24 36
25 254 0
>;
clocks = <&cru PLL_APLLB>;
rockchip,leakage-voltage-sel = <
1 24 0
25 50 1
51 254 2
>;
nvmem-cells = <&cpu_leakage>;
nvmem-cell-names = "cpu_leakage";
opp-216000000 {
opp-hz = /bits/ 64 <216000000>;
opp-microvolt = <950000 950000 1350000>;
opp-microvolt-L0 = <1050000 1050000 1350000>;
opp-microvolt-L1 = <950000 950000 1350000>;
opp-microvolt-L2 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000 950000 1350000>;
opp-microvolt-L0 = <1050000 1050000 1350000>;
opp-microvolt-L1 = <950000 950000 1350000>;
opp-microvolt-L2 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000 950000 1350000>;
opp-microvolt-L0 = <1050000 1050000 1350000>;
opp-microvolt-L1 = <950000 950000 1350000>;
opp-microvolt-L2 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <975000 975000 1350000>;
opp-microvolt-L0 = <1075000 1075000 1350000>;
opp-microvolt-L1 = <975000 975000 1350000>;
opp-microvolt-L2 = <975000 975000 1350000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1050000 1050000 1350000>;
opp-microvolt-L0 = <1150000 1150000 1350000>;
opp-microvolt-L1 = <1050000 1050000 1350000>;
opp-microvolt-L2 = <1025000 1025000 1350000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1150000 1150000 1350000>;
opp-microvolt-L0 = <1250000 1250000 1350000>;
opp-microvolt-L1 = <1150000 1150000 1350000>;
opp-microvolt-L2 = <1125000 1125000 1350000>;
clock-latency-ns = <40000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1225000 1225000 1350000>;
opp-microvolt-L0 = <1350000 1350000 1350000>;
opp-microvolt-L1 = <1225000 1225000 1350000>;
opp-microvolt-L2 = <1200000 1200000 1350000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1300000 1300000 1350000>;
opp-microvolt-L0 = <1350000 1350000 1350000>;
opp-microvolt-L1 = <1300000 1300000 1350000>;
opp-microvolt-L2 = <1275000 1275000 1350000>;
clock-latency-ns = <40000>;
};
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1350000 1350000 1350000>;
opp-microvolt-L0 = <1350000 1350000 1350000>;
opp-microvolt-L1 = <1350000 1350000 1350000>;
opp-microvolt-L2 = <1325000 1325000 1350000>;
clock-latency-ns = <40000>;
};
};