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UPSTREAM: coresight: tmc-etr: Check if non-secure access is enabled

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(Upstream commit 8a4bc4f195).

CoreSight TMC-ETR must have the non-secure invasive debug access
enabled for use by self-hosted tracing. Without it, there is no
point in enabling the ETR. So, let us check it in the TMC_AUTHSTATUS
register and fail the probe if it is disabled.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20190829202842.580-7-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Bug: 140266694
Change-Id: I6f72e88ccf4175bfebb0e237bca63ec59ccc35f8
Signed-off-by: Yabin Cui <yabinc@google.com>
This commit is contained in:
Suzuki K Poulose
2019-08-29 14:28:31 -06:00
committed by Yabin Cui
parent c24fff6d66
commit f071d3702c
2 changed files with 15 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/hwtracing/coresight/coresight-tmc.c
View File

@@ -231,6 +231,7 @@ coresight_tmc_reg(ffcr, TMC_FFCR);
coresight_tmc_reg(mode, TMC_MODE);
coresight_tmc_reg(pscr, TMC_PSCR);
coresight_tmc_reg(axictl, TMC_AXICTL);
coresight_tmc_reg(authstatus, TMC_AUTHSTATUS);
coresight_tmc_reg(devid, CORESIGHT_DEVID);
coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
@@ -250,6 +251,7 @@ static struct attribute *coresight_tmc_mgmt_attrs[] = {
&dev_attr_devid.attr,
&dev_attr_dba.attr,
&dev_attr_axictl.attr,
&dev_attr_authstatus.attr,
NULL,
};
@@ -338,6 +340,13 @@ static inline bool tmc_etr_can_use_sg(struct tmc_drvdata *drvdata)
"arm,scatter-gather");
}
static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata)
{
u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS);
return (auth & TMC_AUTH_NSID_MASK) == 0x3;
}
/* Detect and initialise the capabilities of a TMC ETR */
static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
u32 devid, void *dev_caps)
@@ -346,6 +355,9 @@ static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
u32 dma_mask = 0;
if (!tmc_etr_has_non_secure_access(drvdata))
return -EACCES;
/* Set the unadvertised capabilities */
tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);

3
drivers/hwtracing/coresight/coresight-tmc.h
View File

@@ -39,6 +39,7 @@
#define TMC_ITATBCTR2 0xef0
#define TMC_ITATBCTR1 0xef4
#define TMC_ITATBCTR0 0xef8
#define TMC_AUTHSTATUS 0xfb8
/* register description */
/* TMC_CTL - 0x020 */
@@ -90,6 +91,8 @@
#define TMC_DEVID_AXIAW_SHIFT 17
#define TMC_DEVID_AXIAW_MASK 0x7f
#define TMC_AUTH_NSID_MASK GENMASK(1, 0)
enum tmc_config_type {
TMC_CONFIG_TYPE_ETB,
TMC_CONFIG_TYPE_ETR,