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mmc: sdhci-pci-gli: Add a new function to simplify the code

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[ Upstream commit dec8b38be4b35cae5f7fa086daf2631e2cfa09c1 ]

In preparation to fix replay timer timeout, add
sdhci_gli_mask_replay_timer_timeout() function
to simplify some of the code, allowing it to be re-used.

Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Fixes: 1ae1d2d6e5 ("mmc: sdhci-pci-gli: Add Genesys Logic GL9763E support")
Cc: stable@vger.kernel.org
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20250731065752.450231-2-victorshihgli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Victor Shih
2025-08-23 10:32:44 -04:00
committed by Greg Kroah-Hartman
parent 1eae029f79
commit f0aa8591ba
1 changed files with 16 additions and 14 deletions
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30
drivers/mmc/host/sdhci-pci-gli.c
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@@ -221,6 +221,20 @@
#define GLI_MAX_TUNING_LOOP 40
/* Genesys Logic chipset */
static void sdhci_gli_mask_replay_timer_timeout(struct pci_dev *pdev)
{
int aer;
u32 value;
/* mask the replay timer timeout of AER */
aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
if (aer) {
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
value |= PCI_ERR_COR_REP_TIMER;
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
}
}
static inline void gl9750_wt_on(struct sdhci_host *host)
{
u32 wt_value;
@@ -541,7 +555,6 @@ static void gl9750_hw_setting(struct sdhci_host *host)
{
struct sdhci_pci_slot *slot = sdhci_priv(host);
struct pci_dev *pdev;
int aer;
u32 value;
pdev = slot->chip->pdev;
@@ -563,12 +576,7 @@ static void gl9750_hw_setting(struct sdhci_host *host)
pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
/* mask the replay timer timeout of AER */
aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
if (aer) {
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
value |= PCI_ERR_COR_REP_TIMER;
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
}
sdhci_gli_mask_replay_timer_timeout(pdev);
gl9750_wt_off(host);
}
@@ -743,7 +751,6 @@ static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
{
struct pci_dev *pdev = slot->chip->pdev;
int aer;
u32 value;
gl9755_wt_on(pdev);
@@ -781,12 +788,7 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
/* mask the replay timer timeout of AER */
aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
if (aer) {
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
value |= PCI_ERR_COR_REP_TIMER;
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
}
sdhci_gli_mask_replay_timer_timeout(pdev);
gl9755_wt_off(pdev);
}