shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 10:58:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

video: rockchip: rga3: iommu device uses slave mode

Browse Source 
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I1ab682d3ee687ae13ba4d7c252d1d9ec25875efd
This commit is contained in:
Yu Qiaowei
2022-11-16 20:37:32 +08:00
parent 84d08ffd32
commit f13dae5b9c
3 changed files with 41 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/video/rockchip/rga3/include/rga2_reg_info.h
View File

@@ -4,8 +4,6 @@
#include "rga_drv.h"
#define RGA2_USE_MASTER_MODE 1
#define RGA2_SYS_REG_BASE 0x000
#define RGA2_CSC_REG_BASE 0x060
#define RGA2_CMD_REG_BASE 0x100

20
drivers/video/rockchip/rga3/rga2_reg_info.c
View File

@@ -167,10 +167,6 @@ static void RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg)
if (msg->render_mode == 4)
render_mode = 3;
/* In slave mode, the current frame completion interrupt must be enabled. */
if (!RGA2_USE_MASTER_MODE)
msg->CMD_fin_int_enable = 1;
reg =
((reg & (~m_RGA2_MODE_CTRL_SW_RENDER_MODE)) |
(s_RGA2_MODE_CTRL_SW_RENDER_MODE(render_mode)));
@@ -2268,6 +2264,10 @@ static int rga2_init_reg(struct rga_job *job)
}
}
/* In slave mode, the current frame completion interrupt must be enabled. */
if (scheduler->data->mmu == RGA_IOMMU)
req.CMD_fin_int_enable = 1;
if (rga2_gen_reg_info((uint8_t *)job->cmd_reg, &req) == -1) {
pr_err("gen reg info error\n");
return -EINVAL;
@@ -2411,9 +2411,19 @@ static void rga2_set_reg_full_csc(struct rga_job *job, struct rga_scheduler_t *s
static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
int i;
bool master_mode_en;
uint32_t sys_ctrl;
ktime_t now = ktime_get();
/*
* Currently there is no iova allocated for storing cmd for the IOMMU device,
* so the iommu device needs to use the slave mode.
*/
if (scheduler->data->mmu != RGA_IOMMU)
master_mode_en = true;
else
master_mode_en = false;
if (job->pre_intr_info.enable)
rga2_set_pre_intr_reg(job, scheduler);
@@ -2444,7 +2454,7 @@ static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
m_RGA2_SYS_CTRL_RST_PROTECT_P | m_RGA2_SYS_CTRL_DST_WR_OPT_DIS |
m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS;
if (RGA2_USE_MASTER_MODE) {
if (master_mode_en) {
/* master mode */
sys_ctrl |= s_RGA2_SYS_CTRL_CMD_MODE(1);

40
drivers/video/rockchip/rga3/rga3_reg_info.c
View File

@@ -8,6 +8,7 @@
#define pr_fmt(fmt) "rga3_reg: " fmt
#include "rga3_reg_info.h"
#include "rga_dma_buf.h"
#include "rga_common.h"
#include "rga_debugger.h"
#include "rga_hw_config.h"
@@ -1899,9 +1900,19 @@ static void rga3_dump_read_back_reg(struct rga_scheduler_t *scheduler)
static int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
int i;
bool master_mode_en;
uint32_t sys_ctrl;
ktime_t now = ktime_get();
/*
* Currently there is no iova allocated for storing cmd for the IOMMU device,
* so the iommu device needs to use the slave mode.
*/
if (scheduler->data->mmu != RGA_IOMMU)
master_mode_en = true;
else
master_mode_en = false;
if (DEBUGGER_EN(REG)) {
uint32_t *p;
@@ -1917,24 +1928,25 @@ static int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
rga_write(m_RGA3_INT_FRM_DONE | m_RGA3_INT_CMD_LINE_FINISH | m_RGA3_INT_ERROR_MASK,
RGA3_INT_EN, scheduler);
#if 0
/* master mode */
sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(1);
if (master_mode_en) {
/* master mode */
sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(1);
rga_dma_flush_range(&job->cmd_reg[0], &job->cmd_reg[50], scheduler);
/* cmd buffer flush cache to ddr */
rga_dma_sync_flush_range(&job->cmd_reg[0], &job->cmd_reg[50], scheduler);
rga_write(virt_to_phys(job->cmd_reg), RGA3_CMD_ADDR, scheduler);
rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
rga_write(m_RGA3_CMD_CTRL_CMD_LINE_ST_P, RGA3_CMD_CTRL, scheduler);
#else
/* slave mode */
sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(0) | m_RGA3_SYS_CTRL_RGA_SART;
rga_write(virt_to_phys(job->cmd_reg), RGA3_CMD_ADDR, scheduler);
rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
rga_write(m_RGA3_CMD_CTRL_CMD_LINE_ST_P, RGA3_CMD_CTRL, scheduler);
} else {
/* slave mode */
sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(0) | m_RGA3_SYS_CTRL_RGA_SART;
for (i = 0; i <= 50; i++)
rga_write(job->cmd_reg[i], 0x100 + i * 4, scheduler);
for (i = 0; i <= 50; i++)
rga_write(job->cmd_reg[i], 0x100 + i * 4, scheduler);
rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
#endif
rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
}
if (DEBUGGER_EN(REG)) {
pr_info("sys_ctrl = 0x%x, int_en = 0x%x, int_raw = 0x%x\n",