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ASoC: rockchip: i2s: add a delay before i2s clear

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in order to keep i2s lrck signal integrity, when i2s stop,
need at least one lrck cycle to ensure signal integrity.

the max delay time is when lrck is 8khz, the delay time is
125us(1/8khz), using udelay(150) with a 25us margin.

Change-Id: Ia0b0c8b0153e25ed3686eee2e13f370d0c3da380
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
2017-02-21 11:14:05 +08:00
committed by Huang, Tao
parent bfc4493a96
commit f2217176e0
1 changed files with 2 additions and 0 deletions
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2
sound/soc/rockchip/rockchip_i2s.c
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@@ -117,6 +117,7 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
I2S_XFER_TXS_STOP |
I2S_XFER_RXS_STOP);
udelay(150);
regmap_update_bits(i2s->regmap, I2S_CLR,
I2S_CLR_TXC | I2S_CLR_RXC,
I2S_CLR_TXC | I2S_CLR_RXC);
@@ -163,6 +164,7 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
I2S_XFER_TXS_STOP |
I2S_XFER_RXS_STOP);
udelay(150);
regmap_update_bits(i2s->regmap, I2S_CLR,
I2S_CLR_TXC | I2S_CLR_RXC,
I2S_CLR_TXC | I2S_CLR_RXC);