mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-05 10:31:46 +09:00
Merge tag 'sti-dt-for-v5.15-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into arm/dt
Highlights: ----------- - Introduce 4KOpen STiH418-b2264 board - Remove clk_ignore_unused from STi boards DT - Remove clock-output-names and clk_critical properties - Update some clock compatible * tag 'sti-dt-for-v5.15-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: ARM: dts: sti: remove clk_ignore_unused from bootargs for stih410-b2260 ARM: dts: sti: remove clk_ignore_unused from bootargs for stih418-b2199 ARM: dts: sti: remove clk_ignore_unused from bootargs for stih410-b2120 ARM: dts: sti: remove clk_ignore_unused from bootargs for stih407-b2120 ARM: dts: sti: Introduce 4KOpen (stih418-b2264) board ARM: dts: sti: add the thermal sensor node within stih418 ARM: dts: sti: disable rng11 on the stih418 platform ARM: dts: sti: add the spinor controller node within stih407-family ARM: dts: sti: update clkgen-fsyn entries in stih418-clock ARM: dts: sti: update clkgen-fsyn entries in stih410-clock ARM: dts: sti: update clkgen-fsyn entries in stih407-clock ARM: dts: sti: update clkgen-pll entries in stih418-clock ARM: dts: sti: update clkgen-pll entries in stih410-clock ARM: dts: sti: update clkgen-pll entries in stih407-clock ARM: dts: sti: update flexgen compatible within stih410-clock ARM: dts: sti: update flexgen compatible within stih407-clock ARM: dts: sti: update flexgen compatible within stih418-clock Link: https://lore.kernel.org/r/1d95209f-9cb4-47a3-2696-7a93df7cdc05@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -1079,7 +1079,8 @@ dtb-$(CONFIG_ARCH_STI) += \
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stih407-b2120.dtb \
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stih410-b2120.dtb \
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stih410-b2260.dtb \
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stih418-b2199.dtb
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stih418-b2199.dtb \
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stih418-b2264.dtb
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dtb-$(CONFIG_ARCH_STM32) += \
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stm32f429-disco.dtb \
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stm32f469-disco.dtb \
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@@ -11,7 +11,6 @@
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compatible = "st,stih407-b2120", "st,stih407";
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chosen {
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bootargs = "clk_ignore_unused";
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stdout-path = &sbc_serial0;
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};
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@@ -36,8 +36,6 @@
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compatible = "st,stih407-clkgen-plla9";
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clocks = <&clk_sysin>;
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clock-output-names = "clockgen-a9-pll-odf";
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};
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};
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@@ -74,24 +72,18 @@
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0";
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compatible = "st,clkgen-pll0-a0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll-ofd-0";
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clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
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};
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clk_s_a0_flexgen: clk-s-a0-flexgen {
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compatible = "st,flexgen";
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compatible = "st,flexgen", "st,flexgen-stih407-a0";
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#clock-cells = <1>;
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clocks = <&clk_s_a0_pll 0>,
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<&clk_sysin>;
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clock-output-names = "clk-ic-lmi0";
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clock-critical = <CLK_IC_LMI0>;
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};
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};
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@@ -101,12 +93,6 @@
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reg = <0x9103000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-fs0-ch0",
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"clk-s-c0-fs0-ch1",
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"clk-s-c0-fs0-ch2",
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"clk-s-c0-fs0-ch3";
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clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
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};
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clk_s_c0: clockgen-c@9103000 {
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@@ -115,26 +101,21 @@
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clk_s_c0_pll0: clk-s-c0-pll0 {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0";
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compatible = "st,clkgen-pll0-c0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-pll0-odf-0";
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clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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};
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clk_s_c0_pll1: clk-s-c0-pll1 {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll1";
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compatible = "st,clkgen-pll1-c0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-pll1-odf-0";
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};
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clk_s_c0_flexgen: clk-s-c0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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compatible = "st,flexgen", "st,flexgen-stih407-c0";
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clocks = <&clk_s_c0_pll0 0>,
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<&clk_s_c0_pll1 0>,
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@@ -144,45 +125,6 @@
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<&clk_s_c0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-icn-gpu",
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"clk-fdma",
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"clk-nand",
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"clk-hva",
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"clk-proc-stfe",
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"clk-proc-tp",
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"clk-rx-icn-dmu",
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"clk-rx-icn-hva",
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"clk-icn-cpu",
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"clk-tx-icn-dmu",
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"clk-mmc-0",
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"clk-mmc-1",
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"clk-jpegdec",
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"clk-ext2fa9",
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"clk-ic-bdisp-0",
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"clk-ic-bdisp-1",
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"clk-pp-dmu",
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"clk-vid-dmu",
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"clk-dss-lpc",
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"clk-st231-aud-0",
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"clk-st231-gp-1",
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"clk-st231-dmu",
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"clk-icn-lmi",
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"clk-tx-icn-disp-1",
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"clk-icn-sbc",
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"clk-stfe-frc2",
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"clk-eth-phy",
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"clk-eth-ref-phyclk",
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"clk-flash-promip",
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"clk-main-disp",
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"clk-aux-disp",
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"clk-compo-dvp";
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clock-critical = <CLK_PROC_STFE>,
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<CLK_ICN_CPU>,
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<CLK_TX_ICN_DMU>,
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<CLK_EXT2F_A9>,
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<CLK_ICN_LMI>,
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<CLK_ICN_SBC>;
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/*
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* ARM Peripheral clock for timers
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*/
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@@ -202,15 +144,10 @@
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clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
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#clock-cells = <1>;
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compatible = "st,quadfs";
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compatible = "st,quadfs-d0";
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reg = <0x9104000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d0-fs0-ch0",
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"clk-s-d0-fs0-ch1",
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"clk-s-d0-fs0-ch2",
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"clk-s-d0-fs0-ch3";
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};
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clockgen-d0@9104000 {
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@@ -219,32 +156,22 @@
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clk_s_d0_flexgen: clk-s-d0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen-audio", "st,flexgen";
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compatible = "st,flexgen", "st,flexgen-stih407-d0";
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clocks = <&clk_s_d0_quadfs 0>,
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<&clk_s_d0_quadfs 1>,
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<&clk_s_d0_quadfs 2>,
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<&clk_s_d0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-pcm-0",
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"clk-pcm-1",
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"clk-pcm-2",
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"clk-spdiff";
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};
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};
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clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
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#clock-cells = <1>;
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compatible = "st,quadfs";
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compatible = "st,quadfs-d2";
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reg = <0x9106000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d2-fs0-ch0",
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"clk-s-d2-fs0-ch1",
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"clk-s-d2-fs0-ch2",
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"clk-s-d2-fs0-ch3";
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};
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clockgen-d2@9106000 {
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@@ -253,7 +180,7 @@
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clk_s_d2_flexgen: clk-s-d2-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen-video", "st,flexgen";
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compatible = "st,flexgen", "st,flexgen-stih407-d2";
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clocks = <&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>,
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@@ -262,37 +189,15 @@
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<&clk_sysin>,
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<&clk_sysin>,
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<&clk_tmdsout_hdmi>;
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clock-output-names = "clk-pix-main-disp",
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"clk-pix-pip",
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"clk-pix-gdp1",
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"clk-pix-gdp2",
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"clk-pix-gdp3",
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"clk-pix-gdp4",
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"clk-pix-aux-disp",
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"clk-denc",
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"clk-pix-hddac",
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"clk-hddac",
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"clk-sddac",
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"clk-pix-dvo",
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"clk-dvo",
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"clk-pix-hdmi",
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"clk-tmds-hdmi",
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"clk-ref-hdmiphy";
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};
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};
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};
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clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
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#clock-cells = <1>;
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compatible = "st,quadfs";
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compatible = "st,quadfs-d3";
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reg = <0x9107000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d3-fs0-ch0",
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"clk-s-d3-fs0-ch1",
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"clk-s-d3-fs0-ch2",
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"clk-s-d3-fs0-ch3";
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};
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clockgen-d3@9107000 {
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@@ -301,22 +206,13 @@
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clk_s_d3_flexgen: clk-s-d3-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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compatible = "st,flexgen", "st,flexgen-stih407-d3";
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clocks = <&clk_s_d3_quadfs 0>,
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<&clk_s_d3_quadfs 1>,
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<&clk_s_d3_quadfs 2>,
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<&clk_s_d3_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-stfe-frc1",
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"clk-tsout-0",
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"clk-tsout-1",
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"clk-mchi",
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"clk-vsens-compo",
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"clk-frc1-remote",
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"clk-lpc-0",
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"clk-lpc-1";
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};
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};
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};
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@@ -616,6 +616,21 @@
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st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
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};
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spifsm: spifsm@9022000{
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compatible = "st,spi-fsm";
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reg = <0x9022000 0x1000>;
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reg-names = "spi-fsm";
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clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
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clock-names = "emi_clk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fsm>;
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st,syscfg = <&syscfg_core>;
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st,boot-device-reg = <0x8c4>;
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st,boot-device-spi = <0x68>;
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status = "disabled";
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};
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sata0: sata@9b20000 {
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compatible = "st,ahci";
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reg = <0x9b20000 0x1000>;
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@@ -11,7 +11,6 @@
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compatible = "st,stih410-b2120", "st,stih410";
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chosen {
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bootargs = "clk_ignore_unused";
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stdout-path = &sbc_serial0;
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};
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@@ -12,7 +12,6 @@
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compatible = "st,stih410-b2260", "st,stih410";
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chosen {
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bootargs = "clk_ignore_unused";
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stdout-path = &uart1;
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};
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@@ -39,8 +39,6 @@
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compatible = "st,stih407-clkgen-plla9";
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clocks = <&clk_sysin>;
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clock-output-names = "clockgen-a9-pll-odf";
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};
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};
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@@ -74,25 +72,18 @@
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0";
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compatible = "st,clkgen-pll0-a0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll-ofd-0";
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clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
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};
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clk_s_a0_flexgen: clk-s-a0-flexgen {
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compatible = "st,flexgen";
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compatible = "st,flexgen", "st,flexgen-stih410-a0";
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#clock-cells = <1>;
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clocks = <&clk_s_a0_pll 0>,
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<&clk_sysin>;
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clock-output-names = "clk-ic-lmi0",
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"clk-ic-lmi1";
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clock-critical = <CLK_IC_LMI0>;
|
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};
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};
|
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@@ -102,12 +93,6 @@
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reg = <0x9103000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-fs0-ch0",
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"clk-s-c0-fs0-ch1",
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"clk-s-c0-fs0-ch2",
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"clk-s-c0-fs0-ch3";
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clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
|
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};
|
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clk_s_c0: clockgen-c@9103000 {
|
||||
@@ -116,26 +101,21 @@
|
||||
|
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clk_s_c0_pll0: clk-s-c0-pll0 {
|
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#clock-cells = <1>;
|
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compatible = "st,clkgen-pll0";
|
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compatible = "st,clkgen-pll0-c0";
|
||||
|
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clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-c0-pll0-odf-0";
|
||||
clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
|
||||
};
|
||||
|
||||
clk_s_c0_pll1: clk-s-c0-pll1 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgen-pll1";
|
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compatible = "st,clkgen-pll1-c0";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-c0-pll1-odf-0";
|
||||
};
|
||||
|
||||
clk_s_c0_flexgen: clk-s-c0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
compatible = "st,flexgen", "st,flexgen-stih410-c0";
|
||||
|
||||
clocks = <&clk_s_c0_pll0 0>,
|
||||
<&clk_s_c0_pll1 0>,
|
||||
@@ -145,52 +125,6 @@
|
||||
<&clk_s_c0_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-icn-gpu",
|
||||
"clk-fdma",
|
||||
"clk-nand",
|
||||
"clk-hva",
|
||||
"clk-proc-stfe",
|
||||
"clk-proc-tp",
|
||||
"clk-rx-icn-dmu",
|
||||
"clk-rx-icn-hva",
|
||||
"clk-icn-cpu",
|
||||
"clk-tx-icn-dmu",
|
||||
"clk-mmc-0",
|
||||
"clk-mmc-1",
|
||||
"clk-jpegdec",
|
||||
"clk-ext2fa9",
|
||||
"clk-ic-bdisp-0",
|
||||
"clk-ic-bdisp-1",
|
||||
"clk-pp-dmu",
|
||||
"clk-vid-dmu",
|
||||
"clk-dss-lpc",
|
||||
"clk-st231-aud-0",
|
||||
"clk-st231-gp-1",
|
||||
"clk-st231-dmu",
|
||||
"clk-icn-lmi",
|
||||
"clk-tx-icn-disp-1",
|
||||
"clk-icn-sbc",
|
||||
"clk-stfe-frc2",
|
||||
"clk-eth-phy",
|
||||
"clk-eth-ref-phyclk",
|
||||
"clk-flash-promip",
|
||||
"clk-main-disp",
|
||||
"clk-aux-disp",
|
||||
"clk-compo-dvp",
|
||||
"clk-tx-icn-hades",
|
||||
"clk-rx-icn-hades",
|
||||
"clk-icn-reg-16",
|
||||
"clk-pp-hades",
|
||||
"clk-clust-hades",
|
||||
"clk-hwpe-hades",
|
||||
"clk-fc-hades";
|
||||
clock-critical = <CLK_PROC_STFE>,
|
||||
<CLK_ICN_CPU>,
|
||||
<CLK_TX_ICN_DMU>,
|
||||
<CLK_EXT2F_A9>,
|
||||
<CLK_ICN_LMI>,
|
||||
<CLK_ICN_SBC>;
|
||||
|
||||
/*
|
||||
* ARM Peripheral clock for timers
|
||||
*/
|
||||
@@ -210,15 +144,10 @@
|
||||
|
||||
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
compatible = "st,quadfs-d0";
|
||||
reg = <0x9104000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d0-fs0-ch0",
|
||||
"clk-s-d0-fs0-ch1",
|
||||
"clk-s-d0-fs0-ch2",
|
||||
"clk-s-d0-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d0@9104000 {
|
||||
@@ -227,34 +156,22 @@
|
||||
|
||||
clk_s_d0_flexgen: clk-s-d0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen-audio", "st,flexgen";
|
||||
compatible = "st,flexgen", "st,flexgen-stih410-d0";
|
||||
|
||||
clocks = <&clk_s_d0_quadfs 0>,
|
||||
<&clk_s_d0_quadfs 1>,
|
||||
<&clk_s_d0_quadfs 2>,
|
||||
<&clk_s_d0_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-pcm-0",
|
||||
"clk-pcm-1",
|
||||
"clk-pcm-2",
|
||||
"clk-spdiff",
|
||||
"clk-pcmr10-master",
|
||||
"clk-usb2-phy";
|
||||
};
|
||||
};
|
||||
|
||||
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
compatible = "st,quadfs-d2";
|
||||
reg = <0x9106000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d2-fs0-ch0",
|
||||
"clk-s-d2-fs0-ch1",
|
||||
"clk-s-d2-fs0-ch2",
|
||||
"clk-s-d2-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d2@9106000 {
|
||||
@@ -263,7 +180,7 @@
|
||||
|
||||
clk_s_d2_flexgen: clk-s-d2-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen-video", "st,flexgen";
|
||||
compatible = "st,flexgen", "st,flexgen-stih407-d2";
|
||||
|
||||
clocks = <&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 1>,
|
||||
@@ -272,37 +189,15 @@
|
||||
<&clk_sysin>,
|
||||
<&clk_sysin>,
|
||||
<&clk_tmdsout_hdmi>;
|
||||
|
||||
clock-output-names = "clk-pix-main-disp",
|
||||
"clk-pix-pip",
|
||||
"clk-pix-gdp1",
|
||||
"clk-pix-gdp2",
|
||||
"clk-pix-gdp3",
|
||||
"clk-pix-gdp4",
|
||||
"clk-pix-aux-disp",
|
||||
"clk-denc",
|
||||
"clk-pix-hddac",
|
||||
"clk-hddac",
|
||||
"clk-sddac",
|
||||
"clk-pix-dvo",
|
||||
"clk-dvo",
|
||||
"clk-pix-hdmi",
|
||||
"clk-tmds-hdmi",
|
||||
"clk-ref-hdmiphy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
compatible = "st,quadfs-d3";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d3-fs0-ch0",
|
||||
"clk-s-d3-fs0-ch1",
|
||||
"clk-s-d3-fs0-ch2",
|
||||
"clk-s-d3-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d3@9107000 {
|
||||
@@ -311,22 +206,13 @@
|
||||
|
||||
clk_s_d3_flexgen: clk-s-d3-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
compatible = "st,flexgen", "st,flexgen-stih407-d3";
|
||||
|
||||
clocks = <&clk_s_d3_quadfs 0>,
|
||||
<&clk_s_d3_quadfs 1>,
|
||||
<&clk_s_d3_quadfs 2>,
|
||||
<&clk_s_d3_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-stfe-frc1",
|
||||
"clk-tsout-0",
|
||||
"clk-tsout-1",
|
||||
"clk-mchi",
|
||||
"clk-vsens-compo",
|
||||
"clk-frc1-remote",
|
||||
"clk-lpc-0",
|
||||
"clk-lpc-1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -11,7 +11,6 @@
|
||||
compatible = "st,stih418-b2199", "st,stih418";
|
||||
|
||||
chosen {
|
||||
bootargs = "clk_ignore_unused";
|
||||
stdout-path = &sbc_serial0;
|
||||
};
|
||||
|
||||
|
||||
151
arch/arm/boot/dts/stih418-b2264.dts
Normal file
151
arch/arm/boot/dts/stih418-b2264.dts
Normal file
@@ -0,0 +1,151 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2021 STMicroelectronics
|
||||
* Author: Alain Volmat <avolmat@me.com>
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "stih418.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
/ {
|
||||
model = "STiH418 B2264";
|
||||
compatible = "st,stih418-b2264", "st,stih418";
|
||||
|
||||
chosen {
|
||||
stdout-path = &sbc_serial0;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0xc0000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
/* u-boot puts hpen in SBC dmem at 0xb8 offset */
|
||||
cpu-release-addr = <0x94100b8>;
|
||||
};
|
||||
cpu@1 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
/* u-boot puts hpen in SBC dmem at 0xb8 offset */
|
||||
cpu-release-addr = <0x94100b8>;
|
||||
};
|
||||
cpu@2 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
/* u-boot puts hpen in SBC dmem at 0xb8 offset */
|
||||
cpu-release-addr = <0x94100b8>;
|
||||
};
|
||||
cpu@3 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
/* u-boot puts hpen in SBC dmem at 0xb8 offset */
|
||||
cpu-release-addr = <0x94100b8>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: opp_table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <784000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <784000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <784000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <784000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <784000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
ttyAS0 = &sbc_serial0;
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
soc {
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
green {
|
||||
gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
pin-controller-sbc@961f080 {
|
||||
gmac1 {
|
||||
rgmii1-0 {
|
||||
st,pins {
|
||||
rxd0 = <&pio1 4 ALT1 IN DE_IO 300 CLK_A>;
|
||||
rxd1 = <&pio1 5 ALT1 IN DE_IO 300 CLK_A>;
|
||||
rxd2 = <&pio1 6 ALT1 IN DE_IO 300 CLK_A>;
|
||||
rxd3 = <&pio1 7 ALT1 IN DE_IO 300 CLK_A>;
|
||||
rxdv = <&pio2 0 ALT1 IN DE_IO 300 CLK_A>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
|
||||
st,tx-retime-src = "clkgen";
|
||||
|
||||
snps,reset-gpio = <&pio0 7 0>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&miphy28lp_phy {
|
||||
phy_port0: port@9b22000 {
|
||||
st,sata-gen = <2>; /* SATA GEN3 */
|
||||
st,osc-rdy;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sbc_serial0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spifsm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&st_dwc3 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -39,8 +39,6 @@
|
||||
compatible = "st,stih418-clkgen-plla9";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clockgen-a9-pll-odf";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -75,23 +73,18 @@
|
||||
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgen-pll0";
|
||||
compatible = "st,clkgen-pll0-a0";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-a0-pll-ofd-0";
|
||||
};
|
||||
|
||||
clk_s_a0_flexgen: clk-s-a0-flexgen {
|
||||
compatible = "st,flexgen";
|
||||
compatible = "st,flexgen", "st,flexgen-stih410-a0";
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk_s_a0_pll 0>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-ic-lmi0",
|
||||
"clk-ic-lmi1";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -101,11 +94,6 @@
|
||||
reg = <0x9103000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-c0-fs0-ch0",
|
||||
"clk-s-c0-fs0-ch1",
|
||||
"clk-s-c0-fs0-ch2",
|
||||
"clk-s-c0-fs0-ch3";
|
||||
};
|
||||
|
||||
clk_s_c0: clockgen-c@9103000 {
|
||||
@@ -114,25 +102,21 @@
|
||||
|
||||
clk_s_c0_pll0: clk-s-c0-pll0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgen-pll0";
|
||||
compatible = "st,clkgen-pll0-c0";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-c0-pll0-odf-0";
|
||||
};
|
||||
|
||||
clk_s_c0_pll1: clk-s-c0-pll1 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgen-pll1";
|
||||
compatible = "st,clkgen-pll1-c0";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-c0-pll1-odf-0";
|
||||
};
|
||||
|
||||
clk_s_c0_flexgen: clk-s-c0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
compatible = "st,flexgen", "st,flexgen-stih418-c0";
|
||||
|
||||
clocks = <&clk_s_c0_pll0 0>,
|
||||
<&clk_s_c0_pll1 0>,
|
||||
@@ -142,49 +126,6 @@
|
||||
<&clk_s_c0_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-icn-gpu",
|
||||
"clk-fdma",
|
||||
"clk-nand",
|
||||
"clk-hva",
|
||||
"clk-proc-stfe",
|
||||
"clk-tp",
|
||||
"clk-rx-icn-dmu",
|
||||
"clk-rx-icn-hva",
|
||||
"clk-icn-cpu",
|
||||
"clk-tx-icn-dmu",
|
||||
"clk-mmc-0",
|
||||
"clk-mmc-1",
|
||||
"clk-jpegdec",
|
||||
"clk-icn-reg",
|
||||
"clk-proc-bdisp-0",
|
||||
"clk-proc-bdisp-1",
|
||||
"clk-pp-dmu",
|
||||
"clk-vid-dmu",
|
||||
"clk-dss-lpc",
|
||||
"clk-st231-aud-0",
|
||||
"clk-st231-gp-1",
|
||||
"clk-st231-dmu",
|
||||
"clk-icn-lmi",
|
||||
"clk-tx-icn-1",
|
||||
"clk-icn-sbc",
|
||||
"clk-stfe-frc2",
|
||||
"clk-eth-phyref",
|
||||
"clk-eth-ref-phyclk",
|
||||
"clk-flash-promip",
|
||||
"clk-main-disp",
|
||||
"clk-aux-disp",
|
||||
"clk-compo-dvp",
|
||||
"clk-tx-icn-hades",
|
||||
"clk-rx-icn-hades",
|
||||
"clk-icn-reg-16",
|
||||
"clk-pp-hevc",
|
||||
"clk-clust-hevc",
|
||||
"clk-hwpe-hevc",
|
||||
"clk-fc-hevc",
|
||||
"clk-proc-mixer",
|
||||
"clk-proc-sc",
|
||||
"clk-avsp-hevc";
|
||||
|
||||
/*
|
||||
* ARM Peripheral clock for timers
|
||||
*/
|
||||
@@ -204,15 +145,10 @@
|
||||
|
||||
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
compatible = "st,quadfs-d0";
|
||||
reg = <0x9104000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d0-fs0-ch0",
|
||||
"clk-s-d0-fs0-ch1",
|
||||
"clk-s-d0-fs0-ch2",
|
||||
"clk-s-d0-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d0@9104000 {
|
||||
@@ -221,34 +157,22 @@
|
||||
|
||||
clk_s_d0_flexgen: clk-s-d0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen-audio", "st,flexgen";
|
||||
compatible = "st,flexgen", "st,flexgen-stih410-d0";
|
||||
|
||||
clocks = <&clk_s_d0_quadfs 0>,
|
||||
<&clk_s_d0_quadfs 1>,
|
||||
<&clk_s_d0_quadfs 2>,
|
||||
<&clk_s_d0_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-pcm-0",
|
||||
"clk-pcm-1",
|
||||
"clk-pcm-2",
|
||||
"clk-spdiff",
|
||||
"clk-pcmr10-master",
|
||||
"clk-usb2-phy";
|
||||
};
|
||||
};
|
||||
|
||||
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
compatible = "st,quadfs-d2";
|
||||
reg = <0x9106000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d2-fs0-ch0",
|
||||
"clk-s-d2-fs0-ch1",
|
||||
"clk-s-d2-fs0-ch2",
|
||||
"clk-s-d2-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d2@9106000 {
|
||||
@@ -257,7 +181,7 @@
|
||||
|
||||
clk_s_d2_flexgen: clk-s-d2-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen-video", "st,flexgen";
|
||||
compatible = "st,flexgen", "st,flexgen-stih418-d2";
|
||||
|
||||
clocks = <&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 1>,
|
||||
@@ -266,44 +190,15 @@
|
||||
<&clk_sysin>,
|
||||
<&clk_sysin>,
|
||||
<&clk_tmdsout_hdmi>;
|
||||
|
||||
clock-output-names = "clk-pix-main-disp",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"clk-tmds-hdmi-div2",
|
||||
"clk-pix-aux-disp",
|
||||
"clk-denc",
|
||||
"clk-pix-hddac",
|
||||
"clk-hddac",
|
||||
"clk-sddac",
|
||||
"clk-pix-dvo",
|
||||
"clk-dvo",
|
||||
"clk-pix-hdmi",
|
||||
"clk-tmds-hdmi",
|
||||
"clk-ref-hdmiphy",
|
||||
"", "", "", "", "",
|
||||
"", "", "", "", "",
|
||||
"", "", "", "", "",
|
||||
"", "", "", "", "",
|
||||
"", "", "", "", "",
|
||||
"", "", "", "", "",
|
||||
"", "clk-vp9";
|
||||
};
|
||||
};
|
||||
|
||||
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
compatible = "st,quadfs-d3";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d3-fs0-ch0",
|
||||
"clk-s-d3-fs0-ch1",
|
||||
"clk-s-d3-fs0-ch2",
|
||||
"clk-s-d3-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d3@9107000 {
|
||||
@@ -312,22 +207,13 @@
|
||||
|
||||
clk_s_d3_flexgen: clk-s-d3-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
compatible = "st,flexgen", "st,flexgen-stih407-d3";
|
||||
|
||||
clocks = <&clk_s_d3_quadfs 0>,
|
||||
<&clk_s_d3_quadfs 1>,
|
||||
<&clk_s_d3_quadfs 2>,
|
||||
<&clk_s_d3_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-stfe-frc1",
|
||||
"clk-tsout-0",
|
||||
"clk-tsout-1",
|
||||
"clk-mchi",
|
||||
"clk-vsens-compo",
|
||||
"clk-frc1-remote",
|
||||
"clk-lpc-0",
|
||||
"clk-lpc-1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -27,6 +27,10 @@
|
||||
};
|
||||
|
||||
soc {
|
||||
rng11: rng@8a8a000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_picophy1: phy2@0 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
reg = <0 0>;
|
||||
@@ -104,5 +108,13 @@
|
||||
assigned-clock-parents = <&clk_s_c0_pll1 0>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
};
|
||||
|
||||
thermal@91a0000 {
|
||||
compatible = "st,stih407-thermal";
|
||||
reg = <0x91a0000 0x28>;
|
||||
clock-names = "thermal";
|
||||
clocks = <&clk_sysin>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user