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clk: rockchip: px30: Set max parent rate for pdm fractional divider

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Change-Id: I4a2fc90070d380fed280494784f46005f2b5b18d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-05-07 10:34:45 +08:00
committed by Tao Huang
parent 9019a912de
commit f422b3370a
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/rockchip/clk-px30.c
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@@ -22,6 +22,7 @@
#define PX30_GRF_SOC_STATUS0 0x480
#define PX30_I2S_FRAC_MAX_PRATE 600000000
#define PX30_PDM_FRAC_MAX_PRATE 600000000
enum px30_plls {
apll, dpll, cpll, npll, apll_b_h, apll_b_l,
@@ -558,7 +559,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(27), 0,
PX30_CLKGATE_CON(9), 10, GFLAGS,
&px30_pdm_fracmux, 0),
&px30_pdm_fracmux, PX30_PDM_FRAC_MAX_PRATE),
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(9), 11, GFLAGS),