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drm/msm/disp/dpu: get timing engine status from intf status register

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[ Upstream commit e3969eadc8 ]

Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.

Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/524724/
Link: https://lore.kernel.org/r/1677774797-31063-6-git-send-email-quic_vpolimer@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Stable-dep-of: a7129231ed ("drm/msm/dpu: Set DPU_DATA_HCTL_EN for in INTF_SC7180_MASK")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Vinod Polimera
2023-03-02 22:03:08 +05:30
committed by Greg Kroah-Hartman
parent 74abb8d3cd
commit f4c6e5d734
3 changed files with 16 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View File

@@ -79,7 +79,8 @@
#define INTF_SDM845_MASK (0) #define INTF_SDM845_MASK (0)
#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) #define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED))
#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)

12
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@@ -203,17 +203,19 @@ enum {
/** /**
* INTF sub-blocks * INTF sub-blocks
* @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
* pixel data arrives to this INTF * pixel data arrives to this INTF
* @DPU_INTF_TE INTF block has TE configuration support * @DPU_INTF_TE INTF block has TE configuration support
* @DPU_DATA_HCTL_EN Allows data to be transferred at different rate * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
than video timing * than video timing
* @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
* @DPU_INTF_MAX * @DPU_INTF_MAX
*/ */
enum { enum {
DPU_INTF_INPUT_CTRL = 0x1, DPU_INTF_INPUT_CTRL = 0x1,
DPU_INTF_TE, DPU_INTF_TE,
DPU_DATA_HCTL_EN, DPU_DATA_HCTL_EN,
DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_MAX DPU_INTF_MAX
}; };

8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
View File

@@ -57,6 +57,7 @@
#define INTF_PROG_FETCH_START 0x170 #define INTF_PROG_FETCH_START 0x170
#define INTF_PROG_ROT_START 0x174 #define INTF_PROG_ROT_START 0x174
#define INTF_MUX 0x25C #define INTF_MUX 0x25C
#define INTF_STATUS 0x26C
#define INTF_CFG_ACTIVE_H_EN BIT(29) #define INTF_CFG_ACTIVE_H_EN BIT(29)
#define INTF_CFG_ACTIVE_V_EN BIT(30) #define INTF_CFG_ACTIVE_V_EN BIT(30)
@@ -292,8 +293,13 @@ static void dpu_hw_intf_get_status(
struct intf_status *s) struct intf_status *s)
{ {
struct dpu_hw_blk_reg_map *c = &intf->hw; struct dpu_hw_blk_reg_map *c = &intf->hw;
unsigned long cap = intf->cap->features;
if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))
s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);
else
s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31));
if (s->is_en) { if (s->is_en) {
s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);