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drm/rockchip: dw_hdmi: Add rk356x hdmitx phy pll cfg

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After testing, if use previous hdmitx pll cfg , rk356x some
chips will appear 297M tmds clock output abnormal. After
signal testing, it was decided to update the vendor
recommended pll cfg.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: If1ca2f9e5922c9b95b1d90055640daafcacc2301
This commit is contained in:
Algea Cao
2021-10-25 16:19:27 +08:00
committed by Tao Huang
parent 05332f7eb9
commit f4e8f555a4
1 changed files with 103 additions and 2 deletions
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105
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -260,6 +260,94 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
}
};
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_rk356x[] = {
{
30666000, {
{ 0x00b3, 0x0000 },
{ 0x2153, 0x0000 },
{ 0x40f3, 0x0000 },
},
}, {
36800000, {
{ 0x00b3, 0x0000 },
{ 0x2153, 0x0000 },
{ 0x40a2, 0x0001 },
},
}, {
46000000, {
{ 0x00b3, 0x0000 },
{ 0x2142, 0x0001 },
{ 0x40a2, 0x0001 },
},
}, {
61333000, {
{ 0x0072, 0x0001 },
{ 0x2142, 0x0001 },
{ 0x40a2, 0x0001 },
},
}, {
73600000, {
{ 0x0072, 0x0001 },
{ 0x2142, 0x0001 },
{ 0x4061, 0x0002 },
},
}, {
92000000, {
{ 0x0072, 0x0001 },
{ 0x2145, 0x0002 },
{ 0x4061, 0x0002 },
},
}, {
122666000, {
{ 0x0051, 0x0002 },
{ 0x2145, 0x0002 },
{ 0x4061, 0x0002 },
},
}, {
147200000, {
{ 0x0051, 0x0002 },
{ 0x2145, 0x0002 },
{ 0x4064, 0x0003 },
},
}, {
184000000, {
{ 0x0051, 0x0002 },
{ 0x214c, 0x0003 },
{ 0x4064, 0x0003 },
},
}, {
226666000, {
{ 0x0040, 0x0003 },
{ 0x214c, 0x0003 },
{ 0x4064, 0x0003 },
},
}, {
272000000, {
{ 0x0040, 0x0003 },
{ 0x214c, 0x0003 },
{ 0x5a64, 0x0003 },
},
}, {
340000000, {
{ 0x0040, 0x0002 },
{ 0x3b4c, 0x0003 },
{ 0x5a64, 0x0003 },
},
}, {
600000000, {
{ 0x1a40, 0x0003 },
{ 0x3b4c, 0x0003 },
{ 0x5a64, 0x0003 },
},
}, {
~0UL, {
{ 0x0000, 0x0000 },
{ 0x0000, 0x0000 },
{ 0x0000, 0x0000 },
},
}
};
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = {
{
30666000, {
@@ -349,6 +437,19 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
}
};
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr_rk356x[] = {
/* pixelclk bpp8 bpp10 bpp12 */
{
272000000, { 0x0000, 0x0000, 0x0000 },
}, {
340000000, { 0x0001, 0x0000, 0x0000 },
}, {
600000000, { 0x0000, 0x0000, 0x0000 },
}, {
~0UL, { 0x0000, 0x0000, 0x0000},
}
};
static struct dw_hdmi_phy_config rockchip_phy_config[] = {
/*pixelclk symbol term vlev*/
{ 74250000, 0x8009, 0x0004, 0x0272},
@@ -1527,9 +1628,9 @@ static struct rockchip_hdmi_chip_data rk3568_chip_data = {
static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
.mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.mpll_cfg = rockchip_mpll_cfg_rk356x,
.mpll_cfg_420 = rockchip_mpll_cfg_420,
.cur_ctr = rockchip_cur_ctr,
.cur_ctr = rockchip_cur_ctr_rk356x,
.phy_config = rockchip_phy_config,
.phy_data = &rk3568_chip_data,
.ycbcr_420_allowed = true,