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https://github.com/hardkernel/linux.git
synced 2026-06-08 20:07:46 +09:00
rk610 lvds screen 1024x768 1280x800 update
This commit is contained in:
yzq
@@ -68,6 +68,12 @@ config LCD_A050VL01
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bool "RGB A050VL01"
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config LCD_B101EW05
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bool "RGB lcd panel B101EW05"
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config LCD_HDMI_1280x800
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depends on MFD_RK610
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bool "RGB Hannstar LCD_HDMI_1280X800"
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---help---
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if support RK610, this setting can support dual screen output
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config LCD_HDMI_1024x768
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depends on MFD_RK610
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bool "RGB Hannstar LCD_HDMI_1024X768"
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@@ -22,6 +22,7 @@ obj-$(CONFIG_LCD_CPTCLAA038LA31XE) += lcd_CPTclaa038la31xe.o
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obj-$(CONFIG_LCD_HX8357) += lcd_hx8357.o
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obj-$(CONFIG_LCD_HSD100PXN) += lcd_hsd100pxn.o
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obj-$(CONFIG_LCD_HDMI_1280x800) += lcd_hdmi_1280x800.o
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obj-$(CONFIG_LCD_HDMI_1024x768) += lcd_hdmi_1024x768.o
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obj-$(CONFIG_LCD_HDMI_800x480) += lcd_hdmi_800x480.o
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obj-$(CONFIG_LCD_HSD07PFW1) += lcd_hsd07pfw1.o
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@@ -11,28 +11,28 @@
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/* Base */
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#define OUT_TYPE SCREEN_LVDS
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#define OUT_FORMAT LVDS_8BIT_3
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#define OUT_FORMAT LVDS_8BIT_2
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#define OUT_FACE OUT_D888_P666
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#define OUT_CLK 65000000
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#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
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/* Timing */
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#define H_PW 48 //10
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#define H_BP 88 //100
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#define H_VD 800 //1024
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#define H_FP 40 //210
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#define H_PW 10
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#define H_BP 100
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#define H_VD 1024
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#define H_FP 210
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#define V_PW 3 //10
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#define V_BP 32 //10
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#define V_VD 480 //768
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#define V_FP 13 //18
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#define V_PW 10
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#define V_BP 10
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#define V_VD 768
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#define V_FP 18
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#define LCD_WIDTH 202
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#define LCD_HEIGHT 152
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/* scaler Timing */
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//1920*1080*60
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#define S_OUT_CLK SCALE_RATE(148500000,66000000)
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#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4
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#define S_H_PW 100
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#define S_H_BP 100
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#define S_H_VD 1024
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@@ -47,7 +47,7 @@
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#define S_V_ST 14
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//1920*1080*50
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#define S1_OUT_CLK SCALE_RATE(148500000,54000000)
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#define S1_OUT_CLK SCALE_RATE(148500000,54000000) //m=16 n=11 no=4
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#define S1_H_PW 100
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#define S1_H_BP 100
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#define S1_H_VD 1024
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@@ -60,6 +60,66 @@
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#define S1_H_ST 1757
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#define S1_V_ST 14
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//1280*720*60
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#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4
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#define S2_H_PW 100
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#define S2_H_BP 100
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#define S2_H_VD 1024
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#define S2_H_FP 151
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#define S2_V_PW 5
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#define S2_V_BP 15
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#define S2_V_VD 768
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#define S2_V_FP 12
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#define S2_H_ST 0
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#define S2_V_ST 12
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//1280*720*50
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#define S3_OUT_CLK SCALE_RATE(74250000,54000000) // m=32 n=11 no=4
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#define S3_H_PW 100
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#define S3_H_BP 100
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#define S3_H_VD 1024
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#define S3_H_FP 151
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#define S3_V_PW 5
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#define S3_V_BP 15
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#define S3_V_VD 768
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#define S3_V_FP 12
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#define S3_H_ST 0
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#define S3_V_ST 12
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//720*576*50
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#define S4_OUT_CLK SCALE_RATE(27000000,54375000) //m=145 n=9 no=8
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#define S4_H_PW 100
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#define S4_H_BP 100
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#define S4_H_VD 1024
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#define S4_H_FP 81
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#define S4_V_PW 5
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#define S4_V_BP 15
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#define S4_V_VD 768
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#define S4_V_FP 45
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#define S4_H_ST 435
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#define S4_V_ST 45
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//720*480*60
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#define S5_OUT_CLK SCALE_RATE(27000000,72000000) //m=32 n=3 no=4
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#define S5_H_PW 100
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#define S5_H_BP 100
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#define S5_H_VD 1024
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#define S5_H_FP 81
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#define S5_V_PW 5
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#define S5_V_BP 15
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#define S5_V_VD 768
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#define S5_V_FP 51
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#define S5_H_ST 858
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#define S5_V_ST 45
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/* Other */
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#define DCLK_POL 0
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#define SWAP_RB 0
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@@ -95,6 +155,64 @@ static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
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screen->s_hsync_st = S1_H_ST;
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screen->s_vsync_st = S1_V_ST;
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break;
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case HDMI_1280x720p_60Hz:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S2_OUT_CLK;
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screen->s_hsync_len = S2_H_PW;
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screen->s_left_margin = S2_H_BP;
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screen->s_right_margin = S2_H_FP;
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screen->s_hsync_len = S2_H_PW;
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screen->s_upper_margin = S2_V_BP;
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screen->s_lower_margin = S2_V_FP;
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screen->s_vsync_len = S2_V_PW;
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screen->s_hsync_st = S2_H_ST;
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screen->s_vsync_st = S2_V_ST;
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break;
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case HDMI_1280x720p_50Hz:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S3_OUT_CLK;
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screen->s_hsync_len = S3_H_PW;
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screen->s_left_margin = S3_H_BP;
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screen->s_right_margin = S3_H_FP;
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screen->s_hsync_len = S3_H_PW;
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screen->s_upper_margin = S3_V_BP;
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screen->s_lower_margin = S3_V_FP;
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screen->s_vsync_len = S3_V_PW;
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screen->s_hsync_st = S3_H_ST;
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screen->s_vsync_st = S3_V_ST;
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break;
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case HDMI_720x576p_50Hz_4x3:
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case HDMI_720x576p_50Hz_16x9:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S4_OUT_CLK;
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screen->s_hsync_len = S4_H_PW;
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screen->s_left_margin = S4_H_BP;
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screen->s_right_margin = S4_H_FP;
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screen->s_hsync_len = S4_H_PW;
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screen->s_upper_margin = S4_V_BP;
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screen->s_lower_margin = S4_V_FP;
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screen->s_vsync_len = S4_V_PW;
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screen->s_hsync_st = S4_H_ST;
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screen->s_vsync_st = S4_V_ST;
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break;
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case HDMI_720x480p_60Hz_16x9:
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case HDMI_720x480p_60Hz_4x3:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S5_OUT_CLK;
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screen->s_hsync_len = S5_H_PW;
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screen->s_left_margin = S5_H_BP;
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screen->s_right_margin = S5_H_FP;
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screen->s_hsync_len = S5_H_PW;
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screen->s_upper_margin = S5_V_BP;
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screen->s_lower_margin = S5_V_FP;
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screen->s_vsync_len = S5_V_PW;
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screen->s_hsync_st = S5_H_ST;
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screen->s_vsync_st = S5_V_ST;
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break;
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default :
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printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
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return -1;
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277
drivers/video/display/screen/lcd_hdmi_1280x800.c
Normal file
277
drivers/video/display/screen/lcd_hdmi_1280x800.c
Normal file
@@ -0,0 +1,277 @@
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#include <linux/fb.h>
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#include <linux/delay.h>
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#include <mach/gpio.h>
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#include <mach/iomux.h>
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#include <mach/board.h>
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#include "screen.h"
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#include <linux/hdmi.h>
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#include "../../rk29_fb.h"
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#include "../lcd/rk610_lcd.h"
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/* Base */
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#define OUT_TYPE SCREEN_LVDS
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#define OUT_FORMAT LVDS_8BIT_2
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#define OUT_FACE OUT_D888_P666
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#define OUT_CLK 65000000
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#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
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/* Timing */
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#define H_PW 10
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#define H_BP 10
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#define H_VD 1280
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#define H_FP 20
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#define V_PW 10
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#define V_BP 10
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#define V_VD 800
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#define V_FP 13
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#define LCD_WIDTH 202
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#define LCD_HEIGHT 152
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/* scaler Timing */
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//1920*1080*60
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#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4
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#define S_H_PW 10
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#define S_H_BP 10
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#define S_H_VD 1280
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#define S_H_FP 20
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#define S_V_PW 10
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#define S_V_BP 10
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#define S_V_VD 800
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#define S_V_FP 13
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#define S_H_ST 440
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#define S_V_ST 13
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//1920*1080*50
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#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4
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#define S1_H_PW 10
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#define S1_H_BP 10
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#define S1_H_VD 1280
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#define S1_H_FP 77
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#define S1_V_PW 10
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#define S1_V_BP 10
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#define S1_V_VD 800
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#define S1_V_FP 13
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#define S1_H_ST 459
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#define S1_V_ST 13
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//1280*720*60
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#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4
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#define S2_H_PW 10
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#define S2_H_BP 10
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#define S2_H_VD 1280
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#define S2_H_FP 20
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#define S2_V_PW 10
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#define S2_V_BP 10
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#define S2_V_VD 800
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#define S2_V_FP 13
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#define S2_H_ST 440
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#define S2_V_ST 13
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//1280*720*50
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#define S3_OUT_CLK SCALE_RATE(74250000,57375000) // m=34 n=11 no=4
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#define S3_H_PW 10
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#define S3_H_BP 10
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#define S3_H_VD 1280
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#define S3_H_FP 77
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#define S3_V_PW 10
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#define S3_V_BP 10
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#define S3_V_VD 800
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#define S3_V_FP 13
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#define S3_H_ST 459
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#define S3_V_ST 13
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//720*576*50
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#define S4_OUT_CLK SCALE_RATE(27000000,63281250) //m=75 n=4 no=8
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#define S4_H_PW 10
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#define S4_H_BP 10
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#define S4_H_VD 1280
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#define S4_H_FP 185
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#define S4_V_PW 10
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#define S4_V_BP 10
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#define S4_V_VD 800
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#define S4_V_FP 48
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#define S4_H_ST 81
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#define S4_V_ST 48
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//720*480*60
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#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4
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#define S5_H_PW 10
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#define S5_H_BP 10
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#define S5_H_VD 1280
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#define S5_H_FP 130
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#define S5_V_PW 10
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#define S5_V_BP 10
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#define S5_V_VD 800
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#define S5_V_FP 54
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#define S5_H_ST 476
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#define S5_V_ST 48
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/* Other */
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#define DCLK_POL 0
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#define SWAP_RB 0
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#ifdef CONFIG_HDMI_DUAL_DISP
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static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
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{
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switch(hdmi_resolution){
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case HDMI_1920x1080p_60Hz:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S_OUT_CLK;
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screen->s_hsync_len = S_H_PW;
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screen->s_left_margin = S_H_BP;
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screen->s_right_margin = S_H_FP;
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screen->s_hsync_len = S_H_PW;
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screen->s_upper_margin = S_V_BP;
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screen->s_lower_margin = S_V_FP;
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screen->s_vsync_len = S_V_PW;
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screen->s_hsync_st = S_H_ST;
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screen->s_vsync_st = S_V_ST;
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break;
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case HDMI_1920x1080p_50Hz:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S1_OUT_CLK;
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screen->s_hsync_len = S1_H_PW;
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screen->s_left_margin = S1_H_BP;
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screen->s_right_margin = S1_H_FP;
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screen->s_hsync_len = S1_H_PW;
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screen->s_upper_margin = S1_V_BP;
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screen->s_lower_margin = S1_V_FP;
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screen->s_vsync_len = S1_V_PW;
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screen->s_hsync_st = S1_H_ST;
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screen->s_vsync_st = S1_V_ST;
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break;
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case HDMI_1280x720p_60Hz:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S2_OUT_CLK;
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screen->s_hsync_len = S2_H_PW;
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screen->s_left_margin = S2_H_BP;
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screen->s_right_margin = S2_H_FP;
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screen->s_hsync_len = S2_H_PW;
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screen->s_upper_margin = S2_V_BP;
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screen->s_lower_margin = S2_V_FP;
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screen->s_vsync_len = S2_V_PW;
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screen->s_hsync_st = S2_H_ST;
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screen->s_vsync_st = S2_V_ST;
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break;
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case HDMI_1280x720p_50Hz:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S3_OUT_CLK;
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screen->s_hsync_len = S3_H_PW;
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screen->s_left_margin = S3_H_BP;
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screen->s_right_margin = S3_H_FP;
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screen->s_hsync_len = S3_H_PW;
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screen->s_upper_margin = S3_V_BP;
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screen->s_lower_margin = S3_V_FP;
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screen->s_vsync_len = S3_V_PW;
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screen->s_hsync_st = S3_H_ST;
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screen->s_vsync_st = S3_V_ST;
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break;
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case HDMI_720x576p_50Hz_4x3:
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case HDMI_720x576p_50Hz_16x9:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S4_OUT_CLK;
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screen->s_hsync_len = S4_H_PW;
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screen->s_left_margin = S4_H_BP;
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screen->s_right_margin = S4_H_FP;
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screen->s_hsync_len = S4_H_PW;
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screen->s_upper_margin = S4_V_BP;
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screen->s_lower_margin = S4_V_FP;
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screen->s_vsync_len = S4_V_PW;
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screen->s_hsync_st = S4_H_ST;
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screen->s_vsync_st = S4_V_ST;
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break;
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case HDMI_720x480p_60Hz_16x9:
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case HDMI_720x480p_60Hz_4x3:
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/* Scaler Timing */
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screen->hdmi_resolution = hdmi_resolution;
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screen->s_pixclock = S5_OUT_CLK;
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screen->s_hsync_len = S5_H_PW;
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screen->s_left_margin = S5_H_BP;
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screen->s_right_margin = S5_H_FP;
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screen->s_hsync_len = S5_H_PW;
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screen->s_upper_margin = S5_V_BP;
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screen->s_lower_margin = S5_V_FP;
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||||
screen->s_vsync_len = S5_V_PW;
|
||||
screen->s_hsync_st = S5_H_ST;
|
||||
screen->s_vsync_st = S5_V_ST;
|
||||
break;
|
||||
default :
|
||||
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
|
||||
return -1;
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){}
|
||||
#endif
|
||||
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
|
||||
{
|
||||
/* screen type & face */
|
||||
screen->type = OUT_TYPE;
|
||||
screen->face = OUT_FACE;
|
||||
|
||||
/* Screen size */
|
||||
screen->x_res = H_VD;
|
||||
screen->y_res = V_VD;
|
||||
|
||||
screen->width = LCD_WIDTH;
|
||||
screen->height = LCD_HEIGHT;
|
||||
|
||||
/* Timing */
|
||||
screen->lcdc_aclk = LCDC_ACLK;
|
||||
screen->pixclock = OUT_CLK;
|
||||
screen->left_margin = H_BP;
|
||||
screen->right_margin = H_FP;
|
||||
screen->hsync_len = H_PW;
|
||||
screen->upper_margin = V_BP;
|
||||
screen->lower_margin = V_FP;
|
||||
screen->vsync_len = V_PW;
|
||||
|
||||
/* Pin polarity */
|
||||
screen->pin_hsync = 0;
|
||||
screen->pin_vsync = 0;
|
||||
screen->pin_den = 0;
|
||||
screen->pin_dclk = DCLK_POL;
|
||||
|
||||
/* Swap rule */
|
||||
screen->swap_rb = SWAP_RB;
|
||||
screen->swap_rg = 0;
|
||||
screen->swap_gb = 0;
|
||||
screen->swap_delta = 0;
|
||||
screen->swap_dumy = 0;
|
||||
|
||||
/* Operation function*/
|
||||
screen->init = NULL;
|
||||
screen->standby = NULL;
|
||||
screen->sscreen_get = set_scaler_info;
|
||||
screen->sscreen_set = rk610_lcd_scaler_set_param;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -26,18 +26,24 @@ enum{
|
||||
|
||||
enum{
|
||||
SCALE_PLL(148500000, 66000000, 16, 9, 4),
|
||||
SCALE_PLL(148500000, 54000000, 16, 11, 4),
|
||||
SCALE_PLL(148500000, 57375000, 17, 11, 4),
|
||||
SCALE_PLL(148500000, 54000000, 16, 11, 4),
|
||||
SCALE_PLL(148500000, 33000000, 16, 9, 8),
|
||||
SCALE_PLL(148500000, 30375000, 18, 11, 8),
|
||||
SCALE_PLL(148500000, 29700000, 16, 10, 8),
|
||||
SCALE_PLL(148500000, 25312500, 15, 11, 8),
|
||||
|
||||
SCALE_PLL(74250000, 66000000, 32, 9, 4),
|
||||
SCALE_PLL(74250000, 57375000, 34, 11, 4),
|
||||
SCALE_PLL(74250000, 54000000, 32, 11, 4),
|
||||
SCALE_PLL(74250000, 33000000, 32, 9, 8),
|
||||
SCALE_PLL(74250000, 30375000, 36, 11, 8),
|
||||
SCALE_PLL(74250000, 25312500, 30, 11, 8),
|
||||
|
||||
SCALE_PLL(27000000, 75000000, 100, 9, 4),
|
||||
SCALE_PLL(27000000, 72000000, 32, 3, 4),
|
||||
SCALE_PLL(27000000, 63281250, 75, 4, 8),
|
||||
SCALE_PLL(27000000, 54375000, 145, 9, 8),
|
||||
SCALE_PLL(27000000, 31500000, 28, 3, 8),
|
||||
SCALE_PLL(27000000, 30000000, 80, 9, 8),
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user