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rk: rm include/linux/rockchip/common.h
Change-Id: I94147f5517a0bb83c677b5d9005c590e14d58762 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
@@ -748,34 +748,6 @@ int scpi_ddr_set_auto_self_refresh(u32 en)
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}
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EXPORT_SYMBOL_GPL(scpi_ddr_set_auto_self_refresh);
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int scpi_ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
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struct ddr_bw_info *ddr_bw_ch1)
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{
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struct scpi_data_buf sdata;
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struct rk3368_mbox_msg mdata;
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struct __packed1 {
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u32 status;
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} tx_buf;
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struct __packed2 {
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u32 status;
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struct ddr_bw_info ddr_bw_ch0;
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struct ddr_bw_info ddr_bw_ch1;
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} rx_buf;
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tx_buf.status = 0;
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SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_DDR,
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SCPI_DDR_BANDWIDTH_GET, tx_buf, rx_buf);
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if (scpi_execute_cmd(&sdata))
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return 0;
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memcpy(ddr_bw_ch0, &(rx_buf.ddr_bw_ch0), sizeof(rx_buf.ddr_bw_ch0));
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memcpy(ddr_bw_ch1, &(rx_buf.ddr_bw_ch1), sizeof(rx_buf.ddr_bw_ch1));
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return 0;
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}
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EXPORT_SYMBOL_GPL(scpi_ddr_bandwidth_get);
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int scpi_ddr_get_clk_rate(void)
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{
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struct scpi_data_buf sdata;
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@@ -2,7 +2,6 @@
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#include "camsys_soc_priv.h"
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#include "camsys_gpio.h"
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#include <linux/rockchip/common.h>
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#include <dt-bindings/soc/rockchip-system-status.h>
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#include <soc/rockchip/rockchip-system-status.h>
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#include <linux/rockchip_ion.h>
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@@ -60,7 +60,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
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#include <linux/rockchip/dvfs.h>
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#endif
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#include <linux/rockchip/common.h>
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#include "power.h"
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#include "rk_init_v2.h"
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#include "pvrsrv_device.h"
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@@ -27,7 +27,6 @@
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#include <linux/regmap.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <linux/rockchip/common.h>
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#include <linux/reboot.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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@@ -92,6 +91,7 @@ enum {
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#define MIN_TEMP (-40000)
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#define MAX_TEMP (125000)
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#define INVALID_TEMP INT_MAX
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#define BASE (1024)
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#define BASE_SHIFT (10)
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@@ -33,7 +33,6 @@
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#include <asm/div64.h>
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#include <linux/uaccess.h>
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#include <linux/rockchip/grf.h>
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#include <linux/rockchip/common.h>
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#include <dt-bindings/clock/rk_system_status.h>
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#include <soc/rockchip/rkfb_dmc.h>
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#include <linux/of_gpio.h>
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@@ -31,7 +31,6 @@
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#include <linux/uaccess.h>
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#include <linux/rockchip/cpu.h>
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#include <linux/rockchip/grf.h>
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#include <linux/rockchip/common.h>
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#include <dt-bindings/clock/rk_system_status.h>
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#include "rk3368_lcdc.h"
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@@ -33,7 +33,6 @@
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#include <linux/uaccess.h>
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#include <linux/rockchip/cpu.h>
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#include <linux/rockchip/grf.h>
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#include <linux/rockchip/common.h>
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#include <dt-bindings/clock/rk_system_status.h>
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#include "rk_vop_lite.h"
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@@ -1,95 +0,0 @@
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#ifndef __MACH_ROCKCHIP_COMMON_H
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#define __MACH_ROCKCHIP_COMMON_H
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#include <linux/notifier.h>
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#define RK_DEVICE(VIRT, PHYS, SIZE) \
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{ \
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.virtual = (unsigned long)(VIRT), \
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.pfn = __phys_to_pfn(PHYS), \
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.length = SIZE, \
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.type = MT_DEVICE, \
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}
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extern bool rockchip_jtag_enabled;
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extern unsigned long rockchip_boot_fn;
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extern struct smp_operations rockchip_smp_ops;
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struct ddr_bw_info {
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u32 ddr_wr;
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u32 ddr_rd;
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u32 ddr_act;
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u32 ddr_time;
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u32 ddr_total;
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u32 ddr_percent;
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u32 cpum;
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u32 gpu;
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u32 peri;
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u32 video;
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u32 vio0;
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u32 vio1;
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u32 vio2;
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};
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extern void (*ddr_bandwidth_get)(struct ddr_bw_info *ddr_bw_ch0,
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struct ddr_bw_info *ddr_bw_ch1);
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extern int (*ddr_change_freq)(uint32_t mhz);
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extern long (*ddr_round_rate)(uint32_t mhz);
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extern void (*ddr_set_auto_self_refresh)(bool en);
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extern int (*ddr_recalc_rate)(void);
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int rockchip_cpu_kill(unsigned int cpu);
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void rockchip_cpu_die(unsigned int cpu);
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int rockchip_cpu_disable(unsigned int cpu);
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#define BOOT_MODE_NORMAL 0
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#define BOOT_MODE_FACTORY2 1
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#define BOOT_MODE_RECOVERY 2
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#define BOOT_MODE_CHARGE 3
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#define BOOT_MODE_POWER_TEST 4
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#define BOOT_MODE_OFFMODE_CHARGING 5
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#define BOOT_MODE_REBOOT 6
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#define BOOT_MODE_PANIC 7
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#define BOOT_MODE_WATCHDOG 8
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#define BOOT_MODE_TSADC 9
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int rockchip_boot_mode(void);
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void __init rockchip_boot_mode_init(u32 flag, u32 mode);
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void rockchip_restart_get_boot_mode(const char *cmd, u32 *flag, u32 *mode);
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void __init rockchip_efuse_init(void);
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void __init rockchip_suspend_init(void);
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void __init rockchip_ion_reserve(void);
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void __init rockchip_uboot_mem_reserve(void);
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enum rockchip_pm_policy {
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ROCKCHIP_PM_POLICY_PERFORMANCE = 0,
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ROCKCHIP_PM_POLICY_NORMAL,
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ROCKCHIP_PM_POLICY_POWERSAVE,
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ROCKCHIP_PM_NR_POLICYS,
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};
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enum rockchip_pm_policy rockchip_pm_get_policy(void);
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int rockchip_pm_set_policy(enum rockchip_pm_policy policy);
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int rockchip_pm_policy_register_notifier(struct notifier_block *nb);
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int rockchip_pm_policy_unregister_notifier(struct notifier_block *nb);
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u32 pvtm_get_value(u32 ch, u32 time_us);
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#define INVALID_TEMP INT_MAX
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#if IS_ENABLED(CONFIG_ROCKCHIP_THERMAL)
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int rockchip_tsadc_get_temp(int chn, int voltage);
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#else
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#if IS_ENABLED(CONFIG_SENSORS_ROCKCHIP_TSADC)
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int rockchip_tsadc_get_temp(int chn);
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#else
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static inline int rockchip_tsadc_get_temp(int chn) { return INVALID_TEMP; }
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#endif
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#endif
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#ifdef CONFIG_RK_LAST_LOG
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void rk_last_log_text(char *text, size_t size);
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#else
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static inline void rk_last_log_text(char *text, size_t size) {}
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#endif
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#endif
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@@ -14,8 +14,6 @@
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#ifndef __SOC_ROCKCHIP_SCPI_H
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#define __SOC_ROCKCHIP_SCPI_H
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#include <linux/rockchip/common.h>
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#ifdef CONFIG_RK3368_SCPI_PROTOCOL
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struct scpi_opp_entry {
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u32 freq_hz;
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@@ -46,8 +44,6 @@ int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type);
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int scpi_ddr_send_timing(u32 *p, u32 size);
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int scpi_ddr_round_rate(u32 m_hz);
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int scpi_ddr_set_auto_self_refresh(u32 en);
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int scpi_ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
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struct ddr_bw_info *ddr_bw_ch1);
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int scpi_ddr_get_clk_rate(void);
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int scpi_thermal_get_temperature(void);
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int scpi_thermal_set_clk_cycle(u32 cycle);
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@@ -133,12 +129,6 @@ static inline int scpi_ddr_set_auto_self_refresh(u32 en)
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return -EPERM;
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}
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static inline int scpi_ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
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struct ddr_bw_info *ddr_bw_ch1)
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{
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return -EPERM;
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}
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static inline int scpi_ddr_get_clk_rate(void)
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{
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return -EPERM;
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@@ -35,7 +35,6 @@
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#include <linux/skbuff.h>
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#include <linux/fb.h>
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#include <linux/rockchip/grf.h>
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#include <linux/rockchip/common.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mmc/host.h>
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