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sound: changed endian mode of pcm

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and fixed pdm in i2s code clk error for gxl chip

PD#160061: sound: changed endian mode of pcm

and fixed pdm in i2s code clk error for gxl chip

Change-Id: Idb0f8bc32dbe49dafbab73c30ca20491a7e6891a
Signed-off-by: Peipeng Zhao <peipeng.zhao@amlogic.com>
This commit is contained in:
Peipeng Zhao
2018-01-31 15:05:51 +08:00
committed by Jianxin Pan
parent c592259836
commit f5febfdaf8
4 changed files with 30 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/amlogic/clk/gxl/clk_misc.c
View File

@@ -299,7 +299,7 @@ static struct clk_hw *pcm_mclk_hws[] = {
static struct clk_divider pcm_sclk_div = {
.reg = (void *)HHI_PCM_CLK_CNTL,
.shift = 16,
.width = 5,
.width = 6,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "pcm_sclk_div",

6
sound/soc/amlogic/meson/audio_hw_pcm.c
View File

@@ -165,7 +165,7 @@ RESET_FIFO:
aml_audin_write(AUDIN_FIFO1_CTRL,
(1 << 15) | /* urgent request */
(1 << 11) | /* channel */
(4 << 8) | /* endian */
(6 << 8) | /* endian */
(2 << 3) | /* PCMIN input selection */
(1 << 2) | /* load address */
(0 << 1) | /* reset fifo */
@@ -587,7 +587,7 @@ void pcm_master_out_enable(struct snd_pcm_substream *substream, int flag)
(1 << 5) | /* circular buffer */
(0 << 4) | /* use register set 0 always */
(1 << 3) | /* urgent request */
(4 << 0) /* endian */
(6 << 0) /* endian */
);
aml_audin_write(AUDOUT_CTRL,
@@ -605,7 +605,7 @@ void pcm_master_out_enable(struct snd_pcm_substream *substream, int flag)
(1 << 5) | /* circular buffer */
(0 << 4) | /* use register set 0 always */
(1 << 3) | /* urgent request */
(4 << 0) /* endian */
(6 << 0) /* endian */
);
/* pcmout control3 */

49
sound/soc/amlogic/meson/i2s_dai.c
View File

@@ -285,34 +285,35 @@ static int aml_dai_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct aml_i2s *i2s = snd_soc_dai_get_drvdata(dai);
int srate, mclk_rate, ret;
int srate, ret, mclk_rate;
srate = params_rate(params);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
if (i2s->audin_fifo_src == 3) {
mclk_rate = srate * DEFAULT_MCLK_RATIO_SR;
ret = clk_set_rate(dmic_pub->clk_mclk, mclk_rate * 10);
if (ret)
return ret;
ret = clk_set_parent(dmic_pub->clk_pdm,
if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE)
&& (i2s->audin_fifo_src == 3)) {
mclk_rate = srate * DEFAULT_MCLK_RATIO_SR;
ret = clk_set_rate(dmic_pub->clk_mclk, mclk_rate*40);
if (ret)
return ret;
ret = clk_set_parent(dmic_pub->clk_pdm,
dmic_pub->clk_mclk);
if (ret)
return ret;
ret = clk_set_rate(dmic_pub->clk_pdm, mclk_rate/4);
if (ret)
return ret;
return 0;
}
}
if (i2s->old_samplerate != srate) {
if (audio_in_source == 0 || substream->stream
== SNDRV_PCM_STREAM_PLAYBACK) {
i2s->old_samplerate = srate;
mclk_rate = srate * DEFAULT_MCLK_RATIO_SR;
aml_i2s_set_amclk(i2s, mclk_rate);
}
}
if (ret)
return ret;
ret = clk_set_rate(dmic_pub->clk_pdm,
clk_get_rate(dmic_pub->clk_mclk)/160);
if (ret)
return ret;
}
if (i2s->audin_fifo_src == 3) {/*pdm in as audioin*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
|| i2s->old_samplerate == 0)
i2s->old_samplerate = srate;
} else { /*i2s in as audioin*/
if (i2s->old_samplerate != srate)
i2s->old_samplerate = srate;
}
mclk_rate = i2s->old_samplerate * DEFAULT_MCLK_RATIO_SR;
aml_i2s_set_amclk(i2s, mclk_rate);
return 0;
}

2
sound/soc/amlogic/meson/pcm_dai.c
View File

@@ -54,7 +54,7 @@ static int aml_pcm_set_clk(struct aml_pcm *pcm, unsigned long rate)
{
int ret = 0;
ret = clk_set_rate(pcm->clk_mpll, rate * 10);
ret = clk_set_rate(pcm->clk_mpll, rate * 60);
if (ret) {
pr_info("Cannot set pcm mpll\n");
return ret;