video: rockchip: mpp: fix some 8k av1 video crash issue

1.Some 8K frames took more than 200ms to decode,causing software timeout.
Solution:
Increase the software timeout threshold to 500ms

2.After power off av1dec, read/write reg in cache irq causing kernel
crash.
Solution:
There are two irq for av1:
    a. vcd_irq is decode irq what we need to care about.
    b. cache irq what we do not need to care about.
  So disable the cache irq  temporarily.

Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I282b8e0614321b5adf0fac5f31bb88e2bdb2bf6c
This commit is contained in:
Yandong Lin
2022-04-27 20:05:32 +08:00
committed by Tao Huang
parent 032b9a6afe
commit f673a58a7b
2 changed files with 5 additions and 1 deletions

View File

@@ -472,6 +472,7 @@ free_task:
#define AV1_L2_CACHE_SHAPER_CTRL 0x20
#define AV1_L2_CACHE_SHAPER_EN BIT(0)
#define AV1_L2_CACHE_INT_MASK 0x30
#define AV1_L2_CACHE_PP0_Y_CONFIG0 0x84
#define AV1_L2_CACHE_PP0_Y_CONFIG2 0x8c
#define AV1_L2_CACHE_PP0_Y_CONFIG3 0x90
@@ -526,6 +527,9 @@ static int av1dec_set_l2_cache(struct av1dec_dev *dec, struct av1dec_task *task)
val = line_cnt | (max_h << 16);
writel_relaxed(val, dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_PP0_U_CONFIG3);
/* mask cache irq */
writel_relaxed(0xf, dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_INT_MASK);
/* shaper enable */
writel_relaxed(AV1_L2_CACHE_SHAPER_EN,
dec->reg_base[AV1DEC_CLASS_CACHE] + AV1_L2_CACHE_SHAPER_CTRL);

View File

@@ -36,7 +36,7 @@
#include "mpp_common.h"
#include "mpp_iommu.h"
#define MPP_WORK_TIMEOUT_DELAY (200)
#define MPP_WORK_TIMEOUT_DELAY (500)
#define MPP_WAIT_TIMEOUT_DELAY (2000)
/* Use 'v' as magic number */