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rk312x/rk3036: not change aclk_core_div for stability

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In rk312x/rk3036, do not change aclk_core_div for stability.
Also remove some unusued macros and codes.

Signed-off-by: dkl <dkl@rock-chips.com>
This commit is contained in:
dkl
2015-02-26 09:44:34 +08:00
parent 495e499bf8
commit f690bea75f
2 changed files with 43 additions and 43 deletions
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82
drivers/clk/rockchip/clk-pll.c
View File

@@ -178,47 +178,47 @@ static const struct apll_clk_set rk3288_apll_table[] = {
};
static const struct apll_clk_set rk3036_apll_table[] = {
_RK3036_APLL_SET_CLKS(1608, 1, 67, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1584, 1, 66, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1560, 1, 65, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1536, 1, 64, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1512, 1, 63, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1488, 1, 62, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1464, 1, 61, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1440, 1, 60, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1416, 1, 59, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1392, 1, 58, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1368, 1, 57, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1344, 1, 56, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1320, 1, 55, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1296, 1, 54, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1272, 1, 53, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1248, 1, 52, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1200, 1, 50, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1104, 1, 46, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1100, 12, 550, 1, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1008, 1, 84, 2, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1000, 6, 500, 2, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(984, 1, 82, 2, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(960, 1, 80, 2, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(936, 1, 78, 2, 1, 1, 0, 81, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(912, 1, 76, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(900, 4, 300, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(888, 1, 74, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(864, 1, 72, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(840, 1, 70, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(816, 1, 68, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(800, 6, 400, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(700, 6, 350, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(696, 1, 58, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(600, 1, 75, 3, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(504, 1, 63, 3, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(500, 6, 250, 2, 1, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(408, 1, 68, 2, 2, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(312, 1, 52, 2, 2, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(216, 1, 72, 4, 2, 1, 0, 41, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(96, 1, 64, 4, 4, 1, 0, 21, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(0, 1, 0, 1, 1, 1, 0, 21, 41, 41, 21, 21),
_RK3036_APLL_SET_CLKS(1608, 1, 67, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1584, 1, 66, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1560, 1, 65, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1536, 1, 64, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1512, 1, 63, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1488, 1, 62, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1464, 1, 61, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1440, 1, 60, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1416, 1, 59, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1392, 1, 58, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1368, 1, 57, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1344, 1, 56, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1320, 1, 55, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1296, 1, 54, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1272, 1, 53, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1248, 1, 52, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1200, 1, 50, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1104, 1, 46, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1100, 12, 550, 1, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1008, 1, 84, 2, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(1000, 6, 500, 2, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(984, 1, 82, 2, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(960, 1, 80, 2, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(936, 1, 78, 2, 1, 1, 0, 81),
_RK3036_APLL_SET_CLKS(912, 1, 76, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(900, 4, 300, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(888, 1, 74, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(864, 1, 72, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(840, 1, 70, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(816, 1, 68, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(800, 6, 400, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(700, 6, 350, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(696, 1, 58, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(600, 1, 75, 3, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(504, 1, 63, 3, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(500, 6, 250, 2, 1, 1, 0, 41),
_RK3036_APLL_SET_CLKS(408, 1, 68, 2, 2, 1, 0, 41),
_RK3036_APLL_SET_CLKS(312, 1, 52, 2, 2, 1, 0, 41),
_RK3036_APLL_SET_CLKS(216, 1, 72, 4, 2, 1, 0, 41),
_RK3036_APLL_SET_CLKS(96, 1, 64, 4, 4, 1, 0, 21),
_RK3036_APLL_SET_CLKS(0, 1, 0, 1, 1, 1, 0, 21),
};
static const struct pll_clk_set rk3036plus_pll_com_table[] = {

4
drivers/clk/rockchip/clk-pll.h
View File

@@ -384,13 +384,13 @@
#define RK3036_CLK_GATE_CLKID(i) (16 * (i))
#define _RK3036_APLL_SET_CLKS(_mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac, \
_periph_div, _aclk_core_div, _axi_div, _apb_div, _ahb_div) \
_periph_div) \
{ \
.rate = (_mhz) * MHZ, \
.pllcon0 = RK3036_PLL_SET_POSTDIV1(_postdiv1) | RK3036_PLL_SET_FBDIV(_fbdiv), \
.pllcon1 = RK3036_PLL_SET_DSMPD(_dsmpd) | RK3036_PLL_SET_POSTDIV2(_postdiv2) | RK3036_PLL_SET_REFDIV(_refdiv), \
.pllcon2 = RK3036_PLL_SET_FRAC(_frac), \
.clksel1 = RK3036_ACLK_CORE_DIV(RATIO_##_aclk_core_div) | RK3036_CLK_CORE_PERI_DIV(RATIO_##_periph_div), \
.clksel1 = RK3036_CLK_CORE_PERI_DIV(RATIO_##_periph_div), \
.lpj = (CLK_LOOPS_JIFFY_REF * _mhz) / CLK_LOOPS_RATE_REF, \
.rst_dly = 0,\
}