vlock: pretect display pll set in vlock [1/1]

PD#TV-3683 Problem: 1.pretect display pll set in vlock, m and frac value write at the sametime. Solution: 1.optmis vlock flow 2.add notify_callback when mode change Verify: tl1 Change-Id: I72fab117c5b7247659c5c08eeff62fbc4d421839 Signed-off-by: Yong Qin <yong.qin@amlogic.com> Conflicts: drivers/amlogic/media/enhancement/amvecm/vlock.c drivers/amlogic/media/enhancement/amvecm/vlock.h
2026-06-10 12:57:06 +09:00 · 2019-03-25 21:01:15 +08:00
parent 8ad280b58f
commit f6c0e8bc88
3 changed files with 183 additions and 71 deletions
--- a/drivers/amlogic/media/enhancement/amvecm/amvecm.c
+++ b/drivers/amlogic/media/enhancement/amvecm/amvecm.c
@@ -31,6 +31,8 @@
 #include <linux/stat.h>
 #include <linux/errno.h>
 #include <linux/uaccess.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 /* #include <linux/amlogic/aml_common.h> */
 #include <linux/ctype.h>/* for parse_para_pq */
 #include <linux/vmalloc.h>
@@ -6555,10 +6557,6 @@ static const struct of_device_id aml_vecm_dt_match[] = {
 		.compatible = "amlogic, vecm-tl1",
 		.data = &vecm_dt_tl1,
 	},
-	{
-		.compatible = "amlogic, vecm-tm2",
-		.data = &vecm_dt_tm2,
-	},
 	{},
 };

@@ -6567,6 +6565,8 @@ static void aml_vecm_dt_parse(struct platform_device *pdev)
 	struct device_node *node;
 	unsigned int val;
 	int ret;
+	const struct of_device_id *of_id;
+	struct vecm_match_data_s *matchdata;

 	node = pdev->dev.of_node;
 	/* get integer value */
--- a/drivers/amlogic/media/enhancement/amvecm/vlock.c
+++ b/drivers/amlogic/media/enhancement/amvecm/vlock.c
@@ -81,7 +81,7 @@ static unsigned int pre_input_freq;
 static unsigned int pre_output_freq;
 static unsigned int vlock_dis_cnt;
 static bool vlock_vmode_changed;
-static unsigned int vlock_vmode_change_status;
+static unsigned int vlock_notify_event;
 static unsigned int pre_hiu_reg_m;
 static unsigned int pre_hiu_reg_frac;
 static signed int pre_enc_max_line;
@@ -178,11 +178,6 @@ u32 vlock_get_panel_pll_m(void)
 	return val;
 }

-void vlock_set_panel_pll_m(u32 val)
-{
-	amvecm_hiu_reg_write(hhi_pll_reg_m, val);
-}
-
 u32 vlock_get_panel_pll_frac(void)
 {
 	u32 val;
@@ -191,11 +186,27 @@ u32 vlock_get_panel_pll_frac(void)
 	return val;
 }

-void vlock_set_panel_pll_frac(u32 val)
+void vlock_set_panel_pll_m(u32 val)
 {
-	amvecm_hiu_reg_write(hhi_pll_reg_frac, val);
+	u32 m = val & 0xff;
+
+	/*amvecm_hiu_reg_write(hhi_pll_reg_m, m);*/
+	lcd_vlock_m_update(m);
 }

+void vlock_set_panel_pll_frac(u32 val)
+{
+	u32 frac = val & 0x1ffff;
+
+	/*amvecm_hiu_reg_write(hhi_pll_reg_frac, frac);*/
+	lcd_vlock_farc_update(frac);
+}
+
+void vlock_set_panel_pll(u32 m, u32 frac)
+{
+	vlock_set_panel_pll_m(m);
+	vlock_set_panel_pll_frac(frac);
+}

 /*returen 1: use phase lock*/
 int phase_lock_check(void)
@@ -514,7 +525,7 @@ void vlock_vmode_check(void)
 		hiu_reg_addr = HHI_HDMI_PLL_CNTL2;
 	vinfo = get_current_vinfo();
 	vlock_vmode_changed = 0;
-	if ((vlock_vmode_change_status == VOUT_EVENT_MODE_CHANGE) ||
+	if ((vlock_notify_event == VOUT_EVENT_MODE_CHANGE) ||
 		(pre_hiu_reg_m == 0)) {
 		if (vlock_mode & (VLOCK_MODE_MANUAL_PLL |
 			VLOCK_MODE_AUTO_PLL)) {
@@ -576,14 +587,13 @@ void vlock_vmode_check(void)
 				vinfo->vtotal + 1;
 			vlock_capture_limit <<= 12;
 		}
-		vlock_vmode_change_status = 0;
+		vlock_notify_event = 0;
 		vlock_vmode_changed = 1;
 	}
 }
 static void vlock_disable_step1(void)
 {
 	unsigned int m_reg_value, tmp_value, enc_max_line, enc_max_pixel;
-	unsigned int hiu_reg_addr;

 	/* VLOCK_CNTL_EN disable */
 	vlock_enable(0);
@@ -613,46 +623,32 @@ static void vlock_disable_step1(void)
 				pr_info("restore m value=0x%x\n", tmp_value);
 			}
 			#endif
-
-			#if 1
 			/*restore the orginal pll setting*/
-			/*amvecm_hiu_reg_read(hhi_pll_reg_m, &tmp_value);*/
 			tmp_value = vlock_get_panel_pll_m();
 			m_reg_value = tmp_value & 0xff;
 			if (m_reg_value != (vlock.val_m & 0xff))
 				vlock_set_panel_pll_m(vlock.val_m);
-				/*amvecm_hiu_reg_write(hhi_pll_reg_m,*/
-				/*	vlock.val_m);*/
-
-			/*amvecm_hiu_reg_read(hhi_pll_reg_frac, &tmp_value);*/
 			tmp_value = vlock_get_panel_pll_frac();
 			m_reg_value = tmp_value & 0x1ffff;
 			if (m_reg_value != (vlock.val_frac & 0xfff))
 				vlock_set_panel_pll_frac(vlock.val_frac);
 				/*amvecm_hiu_reg_write(hhi_pll_reg_frac,*/
 				/*	vlock.val_frac);*/
-			pr_info("restore orignal m,f value\n");
-			#endif
+				pr_info("restore orignal m,f value\n");
 		} else {
-			/*amvecm_hiu_reg_read(hhi_pll_reg_frac, &tmp_value);*/
 			tmp_value = vlock_get_panel_pll_frac();
 			m_reg_value = tmp_value & 0xfff;
 			if (m_reg_value != pre_hiu_reg_frac) {
 				tmp_value = (tmp_value & 0xfffff000) |
 					(pre_hiu_reg_frac & 0xfff);
-				/*amvecm_hiu_reg_write(hhi_pll_reg_frac,*/
-				/*	tmp_value);*/
 				vlock_set_panel_pll_frac(tmp_value);
 			}
-			/*amvecm_hiu_reg_read(hhi_pll_reg_m, &tmp_value);*/
 			tmp_value = vlock_get_panel_pll_m();
 			m_reg_value = tmp_value & 0x1ff;
 			if ((m_reg_value != pre_hiu_reg_m) &&
 				(pre_hiu_reg_m != 0)) {
 				tmp_value = (tmp_value & 0xfffffe00) |
 					(pre_hiu_reg_m & 0x1ff);
-				/*amvecm_hiu_reg_write(hhi_pll_reg_m, */
-				/*tmp_value);*/
 				vlock_set_panel_pll_m(tmp_value);
 			}
 		}
@@ -687,6 +683,8 @@ static void vlock_disable_step1(void)
 	}
 	vlock_pll_stable_cnt = 0;
 	vlock_enc_stable_flag = 0;
+	if (vlock_debug & VLOCK_DEBUG_INFO)
+		pr_info(">>>[%s]\n", __func__);
 }

 static bool vlock_disable_step2(void)
@@ -707,13 +705,13 @@ static bool vlock_disable_step2(void)

 		/* disable to adjust pll */
 		WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 29, 1);
-		/* CFG_VID_LOCK_ADJ_EN disable */
-		WRITE_VPP_REG_BITS(ENCL_MAX_LINE_SWITCH_POINT,
-				0, 13, 1);
 		/* disable to adjust pll */
 		WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 30, 1);
 		/* disable vid_lock_en */
 		WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 31, 1);
+		/* CFG_VID_LOCK_ADJ_EN disable */
+		WRITE_VPP_REG_BITS(ENCL_MAX_LINE_SWITCH_POINT,
+				0, 13, 1);
 		vlock_state = VLOCK_STATE_DISABLE_STEP2_DONE;
 		if (is_meson_gxtvbb_cpu()) {
 			amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL6, &temp_val);
@@ -1034,14 +1032,13 @@ static void vlock_pll_adj_limit_check(unsigned int *pll_val)
 }
 static void vlock_enable_step3_pll(void)
 {
-	unsigned int m_reg_value, tmp_value, abs_val, hiu_reg_addr;
+	unsigned int m_reg_value, tmp_value, abs_val;
 	unsigned int ia, oa, abs_cnt;
 	unsigned int pre_m, new_m, tar_m, org_m;
-
-	if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL)
-		hiu_reg_addr = HHI_HDMI_PLL_CNTL1;
-	else
-		hiu_reg_addr = HHI_HDMI_PLL_CNTL2;
+	u32 m_f_reg_value;
+	static u32 m_diff_cnt, f_diff_cnt;
+	u32 mchang = 0;
+	/*static u32 aaa;*/

 	/*vs_i*/
 	tmp_value = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
@@ -1066,7 +1063,7 @@ static void vlock_enable_step3_pll(void)
 			__func__, vlock_log_delta_vcnt,
 			abs_val, vlock_log_last_ivcnt, vlock_log_last_ovcnt);

-	m_reg_value = READ_VPP_REG(VPU_VLOCK_RO_M_INT_FRAC);
+	m_f_reg_value = READ_VPP_REG(VPU_VLOCK_RO_M_INT_FRAC);
 	if (vlock_log_en && (vlock_log_cnt < vlock_log_size)) {
 		#if 0
 		vlock_log[vlock_log_cnt]->pll_frac =
@@ -1078,14 +1075,13 @@ static void vlock_enable_step3_pll(void)
 		tmp_value = vlock_get_panel_pll_frac();
 		vlock_log[vlock_log_cnt]->pll_frac = tmp_value;

-		/*amvecm_hiu_reg_read(hhi_pll_reg_m, &tmp_value);*/
 		tmp_value = vlock_get_panel_pll_m();
 		vlock_log[vlock_log_cnt]->pll_m = tmp_value;
 		#endif
 		vlock_reg_get();
 		vlock_log_cnt++;
 	}
-	if (m_reg_value == 0) {
+	if (m_f_reg_value == 0) {
 		vlock_state = VLOCK_STATE_ENABLE_FORCE_RESET;
 		if (vlock_debug & VLOCK_DEBUG_INFO)
 			pr_info("%s:vlock pll work abnormal! force reset vlock\n",
@@ -1093,7 +1089,8 @@ static void vlock_enable_step3_pll(void)
 		return;
 	}
 	/*check adjust delta limit*/
-	vlock_pll_adj_limit_check(&m_reg_value);
+	if (vlock.dtdata->vlk_hwver < vlock_hw_ver2)
+		vlock_pll_adj_limit_check(&m_f_reg_value);

 	/*vlsi suggest config:don't enable load signal,
 	 *on gxtvbb this load signal will effect SSG,
@@ -1122,8 +1119,70 @@ static void vlock_enable_step3_pll(void)
 			pr_info("%s:vlock input cnt abnormal!!\n", __func__);
 		return;
 	}
+
+	/*m*/
+	tmp_value = vlock_get_panel_pll_m();
+	if (vlock.dtdata->vlk_hwver < vlock_hw_ver2) {
+		abs_val = abs(((m_f_reg_value >> 16) & 0xff) -
+			(pre_hiu_reg_m & 0xff));
+		if ((abs_val > vlock_log_delta_m) &&
+			(vlock_log_delta_en&(1<<4)))
+			pr_info("vlock m delta:%d(0x%x,0x%x)\n",
+				abs_val, ((m_f_reg_value >> 16) & 0x1ff),
+				(tmp_value & 0x1ff));
+		if ((abs_val <= vlock_pll_m_limit) &&
+			(((m_f_reg_value >> 16) & 0x1ff) !=
+				(tmp_value & 0x1ff)) &&
+			(abs_cnt > vlock_delta_cnt_limit)) {
+			tmp_value = (tmp_value & 0xfffffe00) |
+				((m_f_reg_value >> 16) & 0x1ff);
+			vlock_set_panel_pll_m(tmp_value);
+			vlock_pll_val_last &= 0x0000ffff;
+			vlock_pll_val_last |= (m_f_reg_value & 0xffff0000);
+		}
+	} else {
+		pre_m = (tmp_value & 0xff);
+		new_m = ((m_f_reg_value >> 16) & 0x1ff);
+		org_m = (vlock.val_m & 0xff);
+		if ((pre_m != new_m) && (m_diff_cnt++ > VLOCK_UPDATE_M_CNT)) {
+			m_diff_cnt = 0;
+			if (new_m > pre_m) {
+				tar_m = ((pre_m + 1) <
+					(org_m + 1))?(pre_m + 1):(org_m + 1);
+			} else {
+				/*tar_m < pre_m*/
+				tar_m = ((pre_m - 1) <
+					(org_m - 1))?(org_m - 1):(pre_m - 1);
+			}
+			m_reg_value = (tmp_value & 0xffffff00) + tar_m;
+			if (tar_m != (tmp_value & 0xffffff00)) {
+				vlock_set_panel_pll_m(m_reg_value);
+				mchang = 1;
+				if (vlock_debug & VLOCK_DEBUG_INFO)
+					pr_info("vlock m: pre=0x%x, rp=0x%x, wr=0x%x\n",
+					pre_m, new_m, m_reg_value);
+			}
+			#if 0
+			/*for test*/
+			pr_info("vlock m: 0x%x (%d)\n", vlock.val_m, aaa);
+			if (aaa == 0) {
+				aaa = 1;
+				vlock_set_panel_pll_m(vlock.val_m + 1);
+			} else if (aaa == 1) {
+				aaa = 2;
+				vlock_set_panel_pll_m(vlock.val_m);
+			} else if (aaa == 2) {
+				aaa = 3;
+				vlock_set_panel_pll_m(vlock.val_m - 1);
+			} else if (aaa == 3) {
+				aaa = 0;
+				vlock_set_panel_pll_m(vlock.val_m);
+			}
+			#endif
+		}
+	}
+
 	/*frac*/
-	/*amvecm_hiu_reg_read(hhi_pll_reg_frac, &tmp_value);*/
 	tmp_value = vlock_get_panel_pll_frac();
 	if (vlock.dtdata->vlk_hwver < vlock_hw_ver2) {
 		abs_val = abs(((m_f_reg_value & 0xfff) >> 2) -
@@ -1136,7 +1195,7 @@ static void vlock_enable_step3_pll(void)
 		if ((abs_val >= vlock_delta_limit) &&
 			(abs_cnt > vlock_delta_cnt_limit)) {
 			tmp_value = (tmp_value & 0xfffff000) |
-				((m_reg_value & 0xfff) >> 2);
+				((m_f_reg_value & 0xfff) >> 2);
 			/*amvecm_hiu_reg_write(hhi_pll_reg_frac, tmp_value);*/
 			vlock_set_panel_pll_frac(tmp_value);
 			vlock_pll_val_last &= 0xffff0000;
@@ -1203,6 +1262,7 @@ void amve_vlock_process(struct vframe_s *vf)
 	vlock_dis_cnt_no_vf = 0;
 	if (vecm_latch_flag & FLAG_VLOCK_EN) {
 		vlock_enable_step1(vf, vinfo, input_hz, output_hz);
+		vlock_state = VLOCK_STATE_ENABLE_STEP1_DONE;
 		vlock_en = 1;
 		vecm_latch_flag &= ~FLAG_VLOCK_EN;
 	}
@@ -1227,7 +1287,7 @@ void amve_vlock_process(struct vframe_s *vf)
 					__func__);
 			return;
 		}
-		if (vlock_vmode_change_status == VOUT_EVENT_MODE_CHANGE_PRE) {
+		if (vlock_notify_event == VOUT_EVENT_MODE_CHANGE_PRE) {
 			vlock_enable(0);
 			if (vlock_debug & VLOCK_DEBUG_INFO)
 				pr_info("[%s]auto disable vlock module for vmode change pre case!!!\n",
@@ -1240,8 +1300,10 @@ void amve_vlock_process(struct vframe_s *vf)
 			(input_hz != pre_input_freq) ||
 			(output_hz != pre_output_freq) ||
 			vlock_vmode_changed ||
-			(vlock_state == VLOCK_STATE_ENABLE_FORCE_RESET))
+			(vlock_state == VLOCK_STATE_ENABLE_FORCE_RESET)) {
 			vlock_enable_step1(vf, vinfo, input_hz, output_hz);
+			vlock_state = VLOCK_STATE_ENABLE_STEP1_DONE;
+		}
 		if ((vlock_sync_limit_flag < 10) &&
 			(vlock_state >= VLOCK_STATE_ENABLE_STEP1_DONE)) {
 			vlock_sync_limit_flag++;
@@ -1252,12 +1314,16 @@ void amve_vlock_process(struct vframe_s *vf)
 				WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 2, 1);
 				WRITE_VPP_REG(VPU_VLOCK_OVWRITE_ACCUM0, 0);
 				WRITE_VPP_REG(VPU_VLOCK_OVWRITE_ACCUM1, 0);
+				if (vlock_debug & VLOCK_DEBUG_INFO)
+					pr_info("amve_vlock_process-0\n");
 			}
 			if ((vlock_sync_limit_flag == 4) &&
 				((vlock_mode & (VLOCK_MODE_MANUAL_ENC |
 				VLOCK_MODE_MANUAL_PLL)))) {
 				WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 5, 1);
 				WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 2, 1);
+				if (vlock_debug & VLOCK_DEBUG_INFO)
+					pr_info("amve_vlock_process-1\n");
 			}
 		}
 		if ((vlock_sync_limit_flag == 5) &&
@@ -1266,16 +1332,19 @@ void amve_vlock_process(struct vframe_s *vf)
 			/*READ_VPP_REG_BITS(VPU_VLOCK_RO_VS_I_DIST,*/
 			/*	0, 28);*/
 			input_vs_cnt = XTAL_VLOCK_CLOCK/input_hz;
-			if (vf->type_original & VIDTYPE_TYPEMASK)
+			/*tl1 not need */
+			if (!cpu_after_eq(MESON_CPU_MAJOR_ID_TL1) &&
+				vf->type_original & VIDTYPE_TYPEMASK)
 				input_vs_cnt = input_vs_cnt << 1;
 			WRITE_VPP_REG(VPU_VLOCK_LOOP1_IMISSYNC_MAX,
 					input_vs_cnt*125/100);
 			WRITE_VPP_REG(VPU_VLOCK_LOOP1_IMISSYNC_MIN,
 					input_vs_cnt*70/100);
 			/*cal accum1 value*/
-			WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 2, 1);
+			/*WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 2, 1);*/
 			/*cal accum0 value*/
-			WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 5, 1);
+			/*WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 5, 1);*/
+			vlock_reset(0);
 			vlock_state = VLOCK_STATE_ENABLE_STEP2_DONE;

 			/*
@@ -1375,6 +1444,10 @@ void vlock_clear_frame_counter(void)
 	vlock.frame_cnt_in = 0;
 	vlock.frame_cnt_no = 0;
 	vlock_log_cnt = 0;
+	vlock.phlock_sts = false;
+	vlock.frqlock_sts = false;
+	vlock.pll_mode_pause = false;
+	/*vlock.frqlock_stable_cnt = 0;*/
 }

 void vlock_set_en(bool en)
@@ -1391,13 +1464,13 @@ void vlock_status_init(void)
 	vlock_mode = VLOCK_MODE_MANUAL_PLL;
 	if (is_meson_gxtvbb_cpu() ||
 		is_meson_txl_cpu() || is_meson_txlx_cpu()
-		|| is_meson_tl1_cpu())
+		|| is_meson_tl1_cpu() || is_meson_tm2_cpu())
 		vlock_en = 1;
 	else
 		vlock_en = 0;

 	/*initial pll register address*/
-	if (is_meson_tl1_cpu()) {
+	if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
 		hhi_pll_reg_m = HHI_TCON_PLL_CNTL0;
 		hhi_pll_reg_frac = HHI_TCON_PLL_CNTL1;
 		/*hhi_pll_reg_vlock_ctl = HHI_HDMI_PLL_VLOCK_CNTL;*/
@@ -1456,7 +1529,13 @@ void vlock_status_init(void)
 	vlock.vf_sts = false;
 	vlock.vmd_chg = false;
 	vlock.md_support = false;
-	vlock.phlock_percent = 40;
+	vlock.fsm_pause = false;
+	vlock.ss_sts = true;
+	vlock.phlock_sts = false;
+	vlock.frqlock_sts = false;
+	vlock.pll_mode_pause = false;
+	vlock.phlock_en = vlock.dtdata->vlk_phlock_en;
+	/* vlock.phlock_percent = phlock_percent; */
 	vlock_clear_frame_counter();


@@ -1479,7 +1558,7 @@ void vlock_set_phase(u32 percent)
 	/*u32 vs_o_val = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);*/
 	u32 data = 0;

-	if (!vlock.dtdata->vlk_phlock_en)
+	if (!vlock.phlock_en)
 		return;

 	if (percent > 100) {
@@ -1490,22 +1569,15 @@ void vlock_set_phase(u32 percent)
 	vlock.phlock_percent = percent;
 	data = (vs_i_val * (100 + vlock.phlock_percent))/200;
 	WRITE_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT, data);
-	pr_info("LOOP1_PHSDIF_TGT:0x%x\n", data);

-	/*reset*/
-	data = READ_VPP_REG(VPU_VLOCK_CTRL);
-	data |= 1 << 2;
-	data |= 1 << 5;
-	WRITE_VPP_REG(VPU_VLOCK_CTRL, data);
-	data &= ~(1 << 2);
-	data &= ~(1 << 5);
-	WRITE_VPP_REG(VPU_VLOCK_CTRL, data);
+	vlock_reset(1);
+	vlock_reset(0);
 }

 void vlock_set_phase_en(u32 en)
 {
 	if (en)
-		vlock.dtdata->vlk_phlock_en = true;
+		vlock.phlock_en = true;
 	else
 		vlock.dtdata->vlk_phlock_en = false;
 	pr_info("vlock phlock_en=%d\n", en);
@@ -1618,7 +1690,7 @@ u32 vlock_fsm_check_support(struct stvlock_sig_sts *pvlock,
 		ret = false;
 	}

-	if (vlock_vmode_change_status == VOUT_EVENT_MODE_CHANGE_PRE) {
+	if (vlock_notify_event == VOUT_EVENT_MODE_CHANGE_PRE) {
 		if (vlock_debug & VLOCK_DEBUG_INFO)
 			pr_info("[%s] for vmode change pre case!!!\n",
 				__func__);
@@ -1654,7 +1726,7 @@ u32 vlock_fsm_input_check(struct stvlock_sig_sts *vlock, struct vframe_s *vf)
 		if (vlock_debug & VLOCK_DEBUG_INFO)
 			pr_info("vlock vfsts chg %d\n", vframe_sts);
 		ret = 1;
-	} else if (vlock_vmode_change_status) {
+	} else if (vlock_notify_event) {
 		/*check video mode status*/
 		vlock->vmd_chg = true;
 		ret = 1;
@@ -1797,12 +1869,15 @@ void vlock_fsm_monitor(struct vframe_s *vf)
 {
 	u32 changed;

+	if (vlock.fsm_pause)
+		return;
+
 	changed = vlock_fsm_input_check(&vlock, vf);
 	switch (vlock.fsm_sts) {
 	case VLOCK_STATE_NULL:
 		if (vlock.vf_sts) {
 			/*have frame in*/
-			if (vlock.frame_cnt_in++ >= 20) {
+			if (vlock.frame_cnt_in++ >= 100) {
 				/*vframe input valid*/
 				if (vlock.md_support) {
 					if (vlock_fsm_to_en_func(&vlock, vf)) {
@@ -2163,6 +2238,7 @@ int vlock_notify_callback(struct notifier_block *block, unsigned long cmd,
 	void *para)
 {
 	const struct vinfo_s *vinfo;
+	u32 cnt = 0;

 	vinfo = get_current_vinfo();
 	if (!vinfo) {
@@ -2172,11 +2248,32 @@ int vlock_notify_callback(struct notifier_block *block, unsigned long cmd,
 	if (vlock_debug & VLOCK_DEBUG_INFO)
 		pr_info("current vmode=%s, vinfo w=%d,h=%d, cmd: 0x%lx\n",
 			vinfo->name, vinfo->width, vinfo->height, cmd);
+
 	switch (cmd) {
 	case VOUT_EVENT_MODE_CHANGE_PRE:
-	case VOUT_EVENT_MODE_CHANGE:
-		vlock_vmode_change_status = cmd;
+		vlock.fsm_pause = true;
+		vlock.fsm_sts = VLOCK_STATE_NULL;
+		vlock_notify_event = cmd;
+		if (vlock.dtdata->vlk_new_fsm &&
+			(vlock.fsm_sts >= VLOCK_STATE_ENABLE_STEP1_DONE) &&
+			(vlock.fsm_sts <= VLOCK_STATE_DISABLE_STEP1_DONE)) {
+			/*stop vlock*/
+			vlock_disable_step1();
+			while (!vlock_disable_step2()) {
+				if (cnt++ > 10)
+					break;
+			}
+		}
+		pr_info("vlock: event MODE_CHANGE_PRE %d\n", cnt);
 		break;
+
+	case VOUT_EVENT_MODE_CHANGE:
+		vlock.fsm_pause = false;
+		vlock.fsm_sts = VLOCK_STATE_NULL;
+		vlock_notify_event = cmd;
+		pr_info("vlock: event MODE_CHANGE\n");
+		break;
+
 	default:
 		break;
 	}
--- a/drivers/amlogic/media/enhancement/amvecm/vlock.h
+++ b/drivers/amlogic/media/enhancement/amvecm/vlock.h
@@ -23,7 +23,7 @@
 #include <linux/amlogic/media/vfm/vframe.h>
 #include "linux/amlogic/media/amvecm/ve.h"

-#define VLOCK_VER "Ref.2019/1/24"
+#define VLOCK_VER "Ref.2019/3/26a"

 #define VLOCK_REG_NUM	33

@@ -62,6 +62,7 @@ enum vlock_param_e {
 struct stvlock_sig_sts {
 	u32 fsm_sts;
 	u32 fsm_prests;
+	u32 fsm_pause;
 	u32 vf_sts;
 	u32 vmd_chg;
 	u32 frame_cnt_in;
@@ -70,6 +71,12 @@ struct stvlock_sig_sts {
 	u32 output_hz;
 	bool md_support;
 	u32 phlock_percent;
+	u32 phlock_sts;
+	u32 phlock_en;
+	u32 frqlock_sts;
+	/*u32 frqlock_stable_cnt;*/
+	u32 ss_sts;
+	u32 pll_mode_pause;
 	struct vecm_match_data_s *dtdata;
 	u32 val_frac;
 	u32 val_m;
@@ -131,6 +138,11 @@ enum VLOCK_MD {
 #define IS_MANUAL_SOFTENC_MODE(md) (md & \
 				VLOCK_MODE_MANUAL_SOFT_ENC)

+#define VLOCK_START_CNT		50
+#define VLOCK_WORK_CNT	(VLOCK_START_CNT + 10)
+
+#define VLOCK_UPDATE_M_CNT	8
+#define VLOCK_UPDATE_F_CNT	4

 #define XTAL_VLOCK_CLOCK   24000000/*vlock use xtal clock*/

@@ -155,7 +167,7 @@ enum VLOCK_MD {
 extern unsigned int vlock_mode;
 extern unsigned int vlock_en;
 extern unsigned int vecm_latch_flag;
-extern void __iomem *amvecm_hiu_reg_base;
+/*extern void __iomem *amvecm_hiu_reg_base;*/
 extern unsigned int probe_ok;

 extern void lcd_ss_enable(bool flag);
@@ -178,4 +190,7 @@ extern void vlock_set_en(bool en);
 extern void vlock_set_phase(u32 percent);
 extern void vlock_set_phase_en(u32 en);

+extern void lcd_vlock_m_update(unsigned int vlock_m);
+extern void lcd_vlock_farc_update(unsigned int vlock_farc);
+extern int lcd_set_ss(unsigned int level, unsigned int freq, unsigned int mode);