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clk: rockchip: Add clock controller for the RV1106

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Add the clock tree definition for the new RV1106 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I392cccbd4a4510940c099b7911a4f4711788f8ee
This commit is contained in:
Elaine Zhang
2022-01-18 11:30:41 +08:00
committed by Tao Huang
parent 33b5055b63
commit f725e9df2c
4 changed files with 1080 additions and 0 deletions
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7
drivers/clk/rockchip/Kconfig
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@@ -16,6 +16,13 @@ config CLK_PX30
help
Build the driver for PX30 Clock Driver.
config CLK_RV1106
tristate "Rockchip RV1106 clock controller support"
depends on ARM || COMPILE_TEST
default y
help
Build the driver for RV1106 Clock Driver.
config CLK_RV1108
tristate "Rockchip RV1108 clock controller support"
depends on ARM || COMPILE_TEST

1
drivers/clk/rockchip/Makefile
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@@ -21,6 +21,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-$(CONFIG_ROCKCHIP_CLK_LINK) += clk-link.o
obj-$(CONFIG_CLK_PX30) += clk-px30.o
obj-$(CONFIG_CLK_RV1106) += clk-rv1106.o
obj-$(CONFIG_CLK_RV1108) += clk-rv1108.o
obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
obj-$(CONFIG_CLK_RK1808) += clk-rk1808.o

1017
drivers/clk/rockchip/clk-rv1106.c Normal file
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File diff suppressed because it is too large Load Diff

55
drivers/clk/rockchip/clk.h
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@@ -78,6 +78,61 @@ struct clk;
#define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
#define PX30_PMU_MODE 0x0020
#define RV1106_TOPCRU_BASE 0x10000
#define RV1106_PERICRU_BASE 0x12000
#define RV1106_VICRU_BASE 0x14000
#define RV1106_NPUCRU_BASE 0x16000
#define RV1106_CORECRU_BASE 0x18000
#define RV1106_VEPUCRU_BASE 0x1A000
#define RV1106_VOCRU_BASE 0x1C000
#define RV1106_DDRCRU_BASE 0x1E000
#define RV1106_SUBDDRCRU_BASE 0x1F000
#define RV1106_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300)
#define RV1106_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800)
#define RV1106_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00)
#define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE)
#define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE)
#define RV1106_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
#define RV1106_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
#define RV1106_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_TOPCRU_BASE)
#define RV1106_GLB_SRST_FST (0xc08 + RV1106_TOPCRU_BASE)
#define RV1106_GLB_SRST_SND (0xc0c + RV1106_TOPCRU_BASE)
#define RV1106_SDIO_CON0 (0xc14 + RV1106_TOPCRU_BASE)
#define RV1106_SDIO_CON1 (0xc18 + RV1106_TOPCRU_BASE)
#define RV1106_SDMMC_CON0 (0xc1c + RV1106_TOPCRU_BASE)
#define RV1106_SDMMC_CON1 (0xc20 + RV1106_TOPCRU_BASE)
#define RV1106_EMMC_CON0 (0xc24 + RV1106_TOPCRU_BASE)
#define RV1106_EMMC_CON1 (0xc28 + RV1106_TOPCRU_BASE)
#define RV1106_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
#define RV1106_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
#define RV1106_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_PERICRU_BASE)
#define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
#define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
#define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
#define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
#define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
#define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
#define RV1106_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
#define RV1106_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
#define RV1106_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_NPUCRU_BASE)
#define RV1106_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
#define RV1106_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
#define RV1106_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_CORECRU_BASE)
#define RV1106_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
#define RV1106_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
#define RV1106_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VEPUCRU_BASE)
#define RV1106_VOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
#define RV1106_VOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
#define RV1106_VOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VOCRU_BASE)
#define RV1106_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
#define RV1106_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
#define RV1106_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_DDRCRU_BASE)
#define RV1106_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
#define RV1106_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
#define RV1106_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_SUBDDRCRU_BASE)
#define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE)
#define RV1108_PLL_CON(x) ((x) * 0x4)
#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)