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hdmitx: eliminate unnecessary print

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PD#156734: hdmitx: eliminate unnecessary print

Change-Id: Id79e6f14367f3c0201d1968a3d61168a47a14e3a
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
This commit is contained in:
Yi Zhou
2018-02-04 19:47:09 +08:00
committed by Yixun Lan
parent 3619351218
commit f773e9ed15
3 changed files with 8 additions and 6 deletions
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10
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
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@@ -3308,10 +3308,13 @@ static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd,
break;
case DDC_HDCP_MUX_INIT:
if (argv == 2) {
/*hdmitx_set_reg_bits
* (HDMITX_TOP_HDCP22_BSOD, 1, 25, 1);
*/
hdmitx_ddc_hw_op(DDC_MUX_DDC);
hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, 1, 6, 1);
udelay(5);
hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_CTRL, 0x6);
hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_CTRL, 0x86);
hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 1, 5, 1);
udelay(10);
hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 0, 5, 1);
@@ -3377,7 +3380,6 @@ static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd,
case DDC_HDCP14_GET_BCAPS_RP:
return !!(hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS3) & (1 << 6));
default:
pr_info(HW "ddc: unknown cmd: 0x%x\n", cmd);
break;
}
return 1;
@@ -3478,7 +3480,7 @@ static int hdmitx_cntl_config(struct hdmitx_dev *hdev, unsigned int cmd,
hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF3, argv, 2, 2);
break;
default:
pr_err(HW "config: unknown cmd: 0x%x\n", cmd);
break;
}
return ret;
@@ -3581,7 +3583,7 @@ static int hdmitx_cntl_misc(struct hdmitx_dev *hdev, unsigned int cmd,
hdmi_hwi_init(hdev);
break;
default:
pr_err(HW "misc: unknown cmd: 0x%x\n", cmd);
break;
}
return 1;
}

2
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_reg.h
View File

@@ -183,7 +183,7 @@ int hdmitx_hdcp_opr(unsigned int val);
#define HDMITX_TOP_AXI_ASYNC_STAT0 (TOP_OFFSET_MASK + 0x027)
#define HDMITX_TOP_I2C_BUSY_CNT_MAX (TOP_OFFSET_MASK + 0x028)
#define HDMITX_TOP_I2C_BUSY_CNT_STAT (TOP_OFFSET_MASK + 0x029)
#define HDMITX_TOP_HDCP22_BSOD (TOP_OFFSET_MASK + 0x02A)
#define HDMITX_TOP_HDCP22_BSOD (TOP_SEC_OFFSET_MASK + 0x02A)
#define HDMITX_TOP_DDC_CNTL (TOP_OFFSET_MASK + 0x02B)
#define HDMITX_TOP_REVOCMEM_ADDR_S (TOP_OFFSET_MASK + 0x2000 >> 2)
#define HDMITX_TOP_REVOCMEM_ADDR_E (TOP_OFFSET_MASK + 0x365E >> 2)

2
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
View File

@@ -70,7 +70,7 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x2a29dc00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);