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drm/rockchip: vop2: fix the core_dclk_div_sel setting

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When the display interface is BT656. the register of
core_dclk_div_sel should always be set 1. Not only 'i'
modes like 480i and 576i, but also 'p' modes like 720p,
both need this setting.

As for BT1120 and other interfaces, this bit should be
1 when display mode belongs to 'i', and 0 when display
mode belongs to 'p'.

Only RK3568 has the core_dclk_div_sel control bit, which
has been removed on RK3588.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: If67614bc5068024d602c6acbbe9676d6245fdf1a
This commit is contained in:
Damon Ding
2022-01-14 14:26:13 +08:00
committed by Tao Huang
parent 2a50bdd537
commit f8882d308d
1 changed files with 8 additions and 1 deletions
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9
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -6151,7 +6151,14 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
VOP_MODULE_SET(vop2, vp, vtotal_pw, vtotal << 16 | vsync_len);
VOP_MODULE_SET(vop2, vp, core_dclk_div, !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
if (vop2->version == VOP_VERSION_RK3568) {
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK ||
vcstate->output_if & VOP_OUTPUT_IF_BT656)
VOP_MODULE_SET(vop2, vp, core_dclk_div, 1);
else
VOP_MODULE_SET(vop2, vp, core_dclk_div, 0);
}
if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420) {
VOP_MODULE_SET(vop2, vp, dclk_div2, 1);
VOP_MODULE_SET(vop2, vp, dclk_div2_phase_lock, 1);