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clk: rockchip: rk3288: always enable gpll_ddr for ddrc.

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When ddr frequency scanning, need to switch to gpll for saving
times.

Change-Id: Ibb7e4ed1fa4babaf65e1d98c8a0891766cea63de
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
This commit is contained in:
Tang Yun ping
2017-05-08 09:36:10 +08:00
committed by Huang, Tao
parent c5ed4570f0
commit f8c67c5e9b
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3288.c
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@@ -306,7 +306,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 8, GFLAGS),
GATE(0, "gpll_ddr", "gpll", 0,
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
RK3288_CLKSEL_CON(26), 2, 1, 0, 0,