shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-03-25 03:50:24 +09:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'release-4.4' of https://github.com/rockchip-linux/kernel into odroidn1-4.4.y

Browse Source
This commit is contained in:
Mauro (mdrjr) Ribeiro
2018-03-05 23:18:57 -03:00
parent 81b1a0e751 eae92ae2b9
commit f93084d632
2014 changed files with 96533 additions and 16928 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
View File

@@ -3,6 +3,7 @@
Required properties:
- compatible: Should be one of the following.
- "rockchip,px30-dfi" - for PX30 SoCs.
- "rockchip,rk3128-dfi" - for RK3128 SoCs.
- "rockchip,rk3288-dfi" - for RK3288 SoCs.
- "rockchip,rk3328-dfi" - for RK3328 SoCs.

2
Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt
View File

@@ -2,7 +2,9 @@
Required properties:
- compatible: Should be one of the following.
- "rockchip,px30-dmc" - for PX30 SoCs.
- "rockchip,rk3128-dmc" - for RK3128 SoCs.
- "rockchip,rk3228-dmc" - for RK3228 SoCs.
- "rockchip,rk3288-dmc" - for RK3288 SoCs.
- "rockchip,rk3328-dmc" - for RK3328 SoCs.
- "rockchip,rk3368-dmc" - for RK3368 SoCs.

10
Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
View File

@@ -1,4 +1,4 @@
Rockchip RK3288 LVDS interface
Rockchip SoCs LVDS interface
================================
Required properties:
@@ -29,10 +29,6 @@ For px30 rgb output:
- pinctrl-names: must contain a "m0" or "m1" entry.
- pinctrl-0: pin control group to be used for this controller.
Optional properties
- pinctrl-names: must contain a "lcdc" entry.
- pinctrl-0: pin control group to be used for this controller.
Required nodes:
The lvds has two video ports as described by
@@ -95,8 +91,6 @@ For Rockchip RK3288:
reg = <0xff96c000 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>;
clock-names = "pclk_lvds";
pinctrl-names = "lcdc";
pinctrl-0 = <&lcdc_ctl>;
avdd1v0-supply = <&vdd10_lcd>;
avdd1v8-supply = <&vcc18_lcd>;
avdd3v3-supply = <&vcca_33>;
@@ -140,8 +134,6 @@ For Rockchip RK3368:
clock-names = "pclk_lvds", "pclk_lvds_ctl";
power-domains = <&power RK3368_PD_VIO>;
rockchip,grf = <&grf>;
pinctrl-names = "lcdc";
pinctrl-0 = <&lcdc_lcdc>;
ports {

4
Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
View File

@@ -11,10 +11,12 @@ Required properties:
MIPI RX0 D-PHY use registers in "general register files", it
should be a child of the GRF.
MIPI TXRX D-PHY have its own registers, it must have a reg property.
MIPI TX1RX1 D-PHY have its own registers, it must have a reg property.
Optional properties:
- reg: offset and length of the register set for the device.
- rockchip,grf: MIPI TX1RX1 D-PHY not only has its own register but also
the GRF, so it is only necessary for MIPI TX1RX1 D-PHY.
port node
-------------------

293
Documentation/devicetree/bindings/mfd/rk809.txt Normal file
View File

@@ -0,0 +1,293 @@
RK809 Power Management Integrated Circuit
Required properties:
- compatible: "rockchip,rk809"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
Optional properties:
- clock-output-names: From common clock binding to override the
default output clock name
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
- vcc3-supply: The input supply for DCDC_REG3
- vcc4-supply: The input supply for DCDC_REG4
- vcc5-supply: The input supply for LDO_REG1, LDO_REG2, LDO_REG3
- vcc6-supply: The input supply for LDO_REG4, LDO_REG5, LDO_REG6
- vcc7-supply: The input supply for LDO_REG7, LDO_REG8, LDO_REG9
- vcc8-supply: The input supply for SWITCH_REG1
- vcc9-supply: The input supply for DCDC_REG5, SWITCH_REG2
Regulators: All the regulators of RK809 to be instantiated shall be
listed in a child node named 'regulators'. Each regulator is represented
by a child node of the 'regulators' node.
regulator-name {
/* standard regulator bindings here */
};
Following regulators of the RK809 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK808 datasheet.
- DCDC_REGn
- valid values for n are 1 to 5.
- LDO_REGn
- valid values for n are 1 to 9.
- SWITCH_REGn
- valid values for n are 1 to 2.
Standard regulator bindings are used inside regulator subnodes. Check
Documentation/devicetree/bindings/regulator/regulator.txt
for more details
Example:
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc5v0_sys: vccsys{
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
rk817_pin0_ts: rk817_pin0_ts {
pins = "gpio0";
function = "pin_fun0";
};
rk817_pin0_gpio: rk817_pin0_gpio {
pins = "gpio0";
function = "gpio";
};
rk817_pin1_gt: rk817_pin1_gt {
pins = "gpio1";
function = "pin_fun0";
};
rk817_pin1_gpio: rk817_pin1_gpio {
pins = "gpio1";
function = "gpio";
};
regulators {
vdd_arm: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <700000>;
};
};
vdd_logic: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <800000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc2v5_ddr: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5_ddr";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v0_soc: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc1v0_soc";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_dvp: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v5_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd1v5_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcc3v3_sys: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_sys";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc3v3_lcd: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_lcd";
};
vcc5v0_host: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc5v0_host";
};
};
};

288
Documentation/devicetree/bindings/mfd/rk817.txt Normal file
View File

@@ -0,0 +1,288 @@
RK817 Power Management Integrated Circuit
Required properties:
- compatible: "rockchip,rk817"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
Optional properties:
- clock-output-names: From common clock binding to override the
default output clock name
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
- vcc3-supply: The input supply for DCDC_REG3
- vcc4-supply: The input supply for DCDC_REG4
- vcc5-supply: The input supply for LDO_REG1, LDO_REG2, LDO_REG3
- vcc6-supply: The input supply for LDO_REG4, LDO_REG5, LDO_REG6
- vcc7-supply: The input supply for LDO_REG7, LDO_REG8, LDO_REG9
- vcc8-supply: The input supply for BOOST
- vcc9-supply: The input supply for OTG_SWITCH
Regulators: All the regulators of RK817 to be instantiated shall be
listed in a child node named 'regulators'. Each regulator is represented
by a child node of the 'regulators' node.
regulator-name {
/* standard regulator bindings here */
};
Following regulators of the RK817 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK808 datasheet.
- DCDC_REGn
- valid values for n are 1 to 4.
- LDO_REGn
- valid values for n are 1 to 9.
Standard regulator bindings are used inside regulator subnodes. Check
Documentation/devicetree/bindings/regulator/regulator.txt
for more details
Example:
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
vcc3-supply = <&vccsys>;
vcc4-supply = <&vccsys>;
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vccsys>;
vcc8-supply = <&vccsys>;
vcc9-supply = <&vccsys>;
vcc10-supply = <&vccsys>;
vcc11-supply = <&vcc_3v0>;
vcc12-supply = <&vcc_3v0>;
vcc13-supply = <&vcc_3v0>;
vcc14-supply = <&vccsys>;
vcc15-supply = <&rk817_boost>;
vccsys: vccsys{
compatible = "regulator-fixed";
regulator-name = "vcc3v8_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
};
rk817_pin0_ts: rk817_pin0_ts {
pins = "gpio0";
function = "pin_fun0";
};
rk817_pin0_gpio: rk817_pin0_gpio {
pins = "gpio0";
function = "gpio";
};
rk817_pin1_gt: rk817_pin1_gt {
pins = "gpio1";
function = "pin_fun0";
};
rk817_pin1_gpio: rk817_pin1_gpio {
pins = "gpio1";
function = "gpio";
};
regulators {
vdd_arm: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <700000>;
};
};
vdd_logic: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <800000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc2v5_ddr: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5_ddr";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v0_soc: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc1v0_soc";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>; //??
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_cif: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_cif";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_cif: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_cif";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v5_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc1v5_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
boost: BOOST {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <4700000>;
regulator-max-microvolt = <5400000>;
regulator-name = "boost";
};
otg_switch: OTG_SWITCH {
regulator-always-on;
regulator-boot-on;
regulator-name = "otg_switch";
};
};
};

37
Documentation/devicetree/bindings/power/rk817-charger.txt Normal file
View File

@@ -0,0 +1,37 @@
rk817-charger
~~~~~~~~~~
Required properties :
- compatible: "rk817,charger"
- min_input_voltage: minimum voltage from adapter
- max_input_current: maximum current from adapter
- max_chrg_current: maximum current for battery charge
- max_chrg_voltage: maximum charge voltage for battery
- chrg_finish_cur: charging termination current
Optional properties :
- virtual_power: test mode for none battery
- power_dc2otg: dc can provide supply for otg 5v
- dc_det_adc: dc detect by saradc
Example:
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
......
charger {
compatible = "rk817,charger";
min_input_voltage = <4500>;
max_input_current = <1500>;
max_chrg_current = <1300>;
max_chrg_voltage = <4200>;
chrg_finish_cur = <300>;
virtual_power = <0>;
dc_det_adc = <0>;
};
......
};

49
Documentation/devicetree/bindings/power_supply/rk817-battery.txt Normal file
View File

@@ -0,0 +1,49 @@
rk817-battery
~~~~~~~~~~
Required properties :
- compatible: "rk817,battery"
- ocv_table: ocv voltage and soc relation table
- design_capacity: real capacity tested by tool
- design_qmax: nominal capacity * 1.1
Optional properties :
- sleep_enter_current: current threshold of enter relax mode
- sleep_exit_current: current threshold of exit relax mode
- sleep_filter_current: current threshold of valid relax mode
- power_off_thresd: vsys voltage threshold of power off
- zero_algorithm_vol: voltage threshold of discharge zero algorithm
- max_soc_offset: soc threshold of correct dsoc as rsoc
- monitor_sec: poll seconds for battery delay work
- virtual_power: test mode for none battery
- energy_mode: try to use all power of battery
Example:
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
......
battery {
compatible = "rk817,battery";
ocv_table = <3400 3654 3686 3710 3744 3775 3803
3825 3843 3858 3870 3886 3955 3988
4010 4023 4032 4049 4080 4151>;
design_capacity = <2000>;
design_qmax = <2200>;
bat_res = <120>;
sleep_enter_current = <300>;
sleep_exit_current = <300>;
sleep_filter_current = <100>;
power_off_thresd = <3500>;
zero_algorithm_vol = <3800>;
max_soc_offset = <60>;
monitor_sec = <5>;
virtual_power = <0>;
energy_mode = <0>;
};
......
};

22
Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt Normal file
View File

@@ -0,0 +1,22 @@
* Rockchip Rk3228 internal codec
Required properties:
- compatible: "rockchip,rk3228-codec"
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
- clock-names: a list of clock names, one for each entry in clocks.
- spk-en-gpio: speaker enable gpio.
- spk-depop-time-ms: speaker depop time msec.
Example for rk3228 internal codec:
codec: codec@12010000 {
compatible = "rockchip,rk3228-codec";
reg = <0x12010000 0x1000>;
clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
clock-names = "mclk", "pclk", "sclk";
spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
status = "disabled";
};

60
Documentation/devicetree/bindings/sound/rockchip,rk817-codec.txt Normal file
View File

@@ -0,0 +1,60 @@
* Rockchip rk817 codec
Required properties:
- compatible: "rockchip,rk817-codec"
- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
- clock-names: should be "mclk".
- spk-volume: DAC L/R volume digital setting for Speaker
- hp-volume: DAC L/R volume digital setting for Headphone
*
* DDAC L/R volume setting
* 0db~-95db,0.375db/step,for example:
* 0: 0dB
* 10: -3.75dB
* 125: -46dB
* 255: -95dB
*
- capture-volume: ADC L/R volume digital setting for Microphone
*
* DADC L/R volume setting
* 0db~-95db,0.375db/step,for example:
* 0: 0dB
* 10: -3.75dB
* 125: -46dB
* 255: -95dB
*
- mic-in-differential:
Boolean. Indicate MIC input are differential, rather than single-ended.
- pdmdata-out-enable:
Boolean. Indicate pdmdata output is enable or disable.
Example for rk817 codec:
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
........
rk817_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk817-codec";
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_mclk>;
hp-volume = <3>;
spk-volume = <3>;
capture-volume = <0>;
mic-in-differential;
status = "okay";
};
........
};

5
Documentation/devicetree/bindings/spi/spi-rockchip.txt
View File

@@ -6,10 +6,11 @@ and display controllers using the SPI communication interface.
Required Properties:
- compatible: should be one of the following.
"rockchip,rk3036-spi" for rk3036 SoCS.
"rockchip,px30-spi" for px30 SoCs.
"rockchip,rk3036-spi" for rk3036 SoCs.
"rockchip,rk3066-spi" for rk3066 SoCs.
"rockchip,rk3188-spi" for rk3188 SoCs.
"rockchip,rk3228-spi" for rk3228 SoCS.
"rockchip,rk3228-spi" for rk3228 SoCs.
"rockchip,rk3288-spi" for rk3288 SoCs.
"rockchip,rk3368-spi" for rk3368 SoCs.
"rockchip,rk3399-spi" for rk3399 SoCs.

28
Documentation/kernel-parameters.txt
View File

@@ -2458,6 +2458,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
nohugeiomap [KNL,x86] Disable kernel huge I/O mappings.
nospectre_v2 [X86] Disable all mitigations for the Spectre variant 2
(indirect branch prediction) vulnerability. System may
allow data leaks with this option, which is equivalent
to spectre_v2=off.
noxsave [BUGS=X86] Disables x86 extended register state save
and restore using xsave. The kernel will fallback to
enabling legacy floating-point and sse state.
@@ -3604,6 +3609,29 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
sonypi.*= [HW] Sony Programmable I/O Control Device driver
See Documentation/laptops/sonypi.txt
spectre_v2= [X86] Control mitigation of Spectre variant 2
(indirect branch speculation) vulnerability.
on - unconditionally enable
off - unconditionally disable
auto - kernel detects whether your CPU model is
vulnerable
Selecting 'on' will, and 'auto' may, choose a
mitigation method at run time according to the
CPU, the available microcode, the setting of the
CONFIG_RETPOLINE configuration option, and the
compiler with which the kernel was built.
Specific mitigations can also be selected manually:
retpoline - replace indirect branches
retpoline,generic - google's original retpoline
retpoline,amd - AMD-specific minimal thunk
Not specifying this option is equivalent to
spectre_v2=auto.
spia_io_base= [HW,MTD]
spia_fio_base=
spia_pedr=

2
Documentation/x86/pti.txt
View File

@@ -78,7 +78,7 @@ this protection comes at a cost:
non-PTI SYSCALL entry code, so requires mapping fewer
things into the userspace page tables. The downside is
that stacks must be switched at entry time.
d. Global pages are disabled for all kernel structures not
c. Global pages are disabled for all kernel structures not
mapped into both kernel and userspace page tables. This
feature of the MMU allows different processes to share TLB
entries mapping the kernel. Losing the feature means more

2
Makefile
View File

@@ -1,6 +1,6 @@
VERSION = 4
PATCHLEVEL = 4
SUBLEVEL = 112
SUBLEVEL = 114
EXTRAVERSION =
NAME = Blurry Fish Butt

1
arch/arm/boot/dts/Makefile
View File

@@ -526,6 +526,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3229-at-gva.dtb \
rk3229-echo-v10.dtb \
rk3229-evb.dtb \
rk3229-evb-android.dtb \
rk3229-gva-sdk.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-android-act8846-edp.dtb \

1
arch/arm/boot/dts/act8846.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
&act8846{

1
arch/arm/boot/dts/act8931.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
&act8931{

10
arch/arm/boot/dts/kirkwood-openblocks_a7.dts
View File

@@ -53,7 +53,8 @@
};
pinctrl: pin-controller@10000 {
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header
&pmx_gpio_header_gpo>;
pinctrl-names = "default";
pmx_uart0: pmx-uart0 {
@@ -85,11 +86,16 @@
* ground.
*/
pmx_gpio_header: pmx-gpio-header {
marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28",
marvell,pins = "mpp17", "mpp29", "mpp28",
"mpp35", "mpp34", "mpp40";
marvell,function = "gpio";
};
pmx_gpio_header_gpo: pxm-gpio-header-gpo {
marvell,pins = "mpp7";
marvell,function = "gpo";
};
pmx_gpio_init: pmx-init {
marvell,pins = "mpp38";
marvell,function = "gpio";

1
arch/arm/boot/dts/rk3036-fpga.dts
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/rkfb/rk_fb.h>
#include "rk3036.dtsi"

1
arch/arm/boot/dts/rk3036-new.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/rkfb/rk_fb.h>
#include "rk3036.dtsi"

1
arch/arm/boot/dts/rk3036-pinctrl.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>

1
arch/arm/boot/dts/rk3036-rk88.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/rkfb/rk_fb.h>
#include "rk3036.dtsi"

1
arch/arm/boot/dts/rk3036-sdk.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/rkfb/rk_fb.h>
#include "rk3036.dtsi"

1
arch/arm/boot/dts/rk3126-86v.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3126.dtsi"

4
arch/arm/boot/dts/rk3126-bnd-d708.dts
View File

@@ -291,9 +291,7 @@
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "disabled";
status = "okay";
};
&gpu {

1
arch/arm/boot/dts/rk3126-cif-sensor.dtsi Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "../../mach-rockchip/rk_camera_sensor_info.h"
/{
rk3126_cif_sensor: rk3126_cif_sensor{

2
arch/arm/boot/dts/rk3126-evb.dts
View File

@@ -351,7 +351,7 @@
&lvds {
status = "okay";
pinctrl-names = "lcdc";
pinctrl-names = "default";
pinctrl-0 = <&lcdc_lcdc>;
ports {
lvds_out: port@1 {

1
arch/arm/boot/dts/rk3126-fpga.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk312x.dtsi"
#include "rk312x-pinctrl.dtsi"

1
arch/arm/boot/dts/rk3126-m708-cif-sensor.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "../../../../drivers/soc/rockchip/rk_camera_sensor_info.h"
/{
cif_sensor: cif_sensor {

1
arch/arm/boot/dts/rk3126-sdk.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3126.dtsi"

1
arch/arm/boot/dts/rk3128-86v.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3128.dtsi"

1
arch/arm/boot/dts/rk3128-box-ns.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3128-box.dts"
/ {

1
arch/arm/boot/dts/rk3128-box-rk88.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3128.dtsi"

1
arch/arm/boot/dts/rk3128-box.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3128.dtsi"

1
arch/arm/boot/dts/rk3128-cif-sensor.dtsi Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "../../mach-rockchip/rk_camera_sensor_info.h"
/{
rk3128_cif_sensor: rk3128_cif_sensor{

2
arch/arm/boot/dts/rk3128-fireprime.dts
View File

@@ -342,7 +342,7 @@
&lvds {
status = "disabled";
pinctrl-names = "lcdc";
pinctrl-names = "default";
pinctrl-0 = <&lcdc_lcdc>;
ports {
lvds_out: port@1 {

1
arch/arm/boot/dts/rk3128-sdk.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3128.dtsi"

4
arch/arm/boot/dts/rk312x-android.dtsi
View File

@@ -129,8 +129,8 @@
reg = <0x88000000 0x1800000>;
};
ramoops_mem: ramoops@68000000 {
reg = <0x68000000 0xf0000>;
ramoops_mem: ramoops@62e00000 {
reg = <0x62e00000 0xf0000>;
};
drm_logo: drm-logo@00000000 {

1
arch/arm/boot/dts/rk312x-pinctrl.dtsi Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>

1
arch/arm/boot/dts/rk312x-sdk.dtsi Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/ {
fiq-debugger {

4
arch/arm/boot/dts/rk312x.dtsi
View File

@@ -214,7 +214,9 @@
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};

1
arch/arm/boot/dts/rk3188-lr097.dts
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3188.dtsi"

1
arch/arm/boot/dts/rk3188-pinctrl.dtsi Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>

1
arch/arm/boot/dts/rk3188-tb.dts
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3188.dtsi"

447
arch/arm/boot/dts/rk3229-evb-android.dts Normal file
View File

@@ -0,0 +1,447 @@
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "rk322x.dtsi"
#include "rk3229-cpu-opp.dtsi"
#include "rk322x-android.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Rockchip RK3229 Evaluation board";
compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
power_key: power-key {
label = "GPIO Key Power";
gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <100>;
wakeup-source;
};
};
hdmi_sound: hdmi-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,hdmi";
simple-audio-card,cpu {
sound-dai = <&i2s0>;
};
simple-audio-card,codec {
sound-dai = <&hdmi>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vccio_1v8_reg: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "vccio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vccio_3v3_reg: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "vccio_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; /* GPIO2_D2 */
};
spdif_out: spdif-out {
status = "okay";
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
spdif-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,name = "ROCKCHIP,SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc_phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vdd_arm: vdd-arm-regulator {
compatible = "pwm-regulator";
rockchip,pwm_id = <1>;
rockchip,pwm_voltage = <1100000>;
pwms = <&pwm1 0 25000 1>;
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
vdd_log: vdd-log-regulator {
compatible = "pwm-regulator";
rockchip,pwm_id = <2>;
rockchip,pwm_voltage = <1200000>;
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6335";
sdio_vref = <1800>;
WIFI,host_wake_irq = <&gpio0 28 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&display_subsystem {
logo-memory-region = <&drm_logo>;
status = "okay";
route {
route_hdmi: route-hdmi {
status = "okay";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_hdmi>;
};
};
};
&dmc {
center-supply = <&vdd_log>;
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_MAC_SRC>;
assigned-clock-rates = <50000000>;
clock_in_out = "output";
phy-supply = <&vcc_phy>;
phy-mode = "rmii";
phy-is-integrated;
status = "okay";
};
&gpu {
status = "okay";
mali-supply = <&vdd_log>;
};
&hdmi {
status = "okay";
#sound-dai-cells = <0>;
ddc-i2c-scl-high-time-ns = <9625>;
ddc-i2c-scl-low-time-ns = <10000>;
rockchip,phy_table =
<165000000 0 0 4 4 4 4>,
<225000000 0 0 6 6 6 6>,
<340000000 1 0 6 10 10 10>,
<594000000 1 0 7 10 10 10>;
};
&io_domains {
status = "okay";
vccio1-supply = <&vccio_3v3_reg>;
vccio2-supply = <&vccio_1v8_reg>;
vccio4-supply = <&vccio_3v3_reg>;
};
&i2c0 {
status = "okay";
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
&i2s0 {
status = "okay";
rockchip,bclk-fs = <128>;
#sound-dai-cells = <0>;
};
&iep {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&pinctrl {
keys {
pwr_key: pwr-key {
rockchip,pins = <3 23 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <1 14 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
status = "okay";
compatible = "rockchip,remotectl-pwm";
remote_pwm_id = <3>;
handle_cpu_id = <1>;
remote_support_psci = <1>;
ir_key1 {
rockchip,usercode = <0x4040>;
rockchip,key_table =
<0xf2 KEY_REPLY>,
<0xba KEY_BACK>,
<0xf4 KEY_UP>,
<0xf1 KEY_DOWN>,
<0xef KEY_LEFT>,
<0xee KEY_RIGHT>,
<0xbd KEY_HOME>,
<0xea KEY_VOLUMEUP>,
<0xe3 KEY_VOLUMEDOWN>,
<0xe2 KEY_SEARCH>,
<0xb2 KEY_POWER>,
<0xbc KEY_MUTE>,
<0xec KEY_MENU>,
<0xbf 0x190>,
<0xe0 0x191>,
<0xe1 0x192>,
<0xe9 183>,
<0xe6 248>,
<0xe8 185>,
<0xe7 186>,
<0xf0 388>,
<0xbe 0x175>;
};
ir_key2 {
rockchip,usercode = <0xff00>;
rockchip,key_table =
<0xf9 KEY_HOME>,
<0xbf KEY_BACK>,
<0xfb KEY_MENU>,
<0xaa KEY_REPLY>,
<0xb9 KEY_UP>,
<0xe9 KEY_DOWN>,
<0xb8 KEY_LEFT>,
<0xea KEY_RIGHT>,
<0xeb KEY_VOLUMEDOWN>,
<0xef KEY_VOLUMEUP>,
<0xf7 KEY_MUTE>,
<0xe7 KEY_POWER>,
<0xfc KEY_POWER>,
<0xa9 KEY_VOLUMEDOWN>,
<0xa8 KEY_PLAYPAUSE>,
<0xe0 KEY_VOLUMEDOWN>,
<0xa5 KEY_VOLUMEDOWN>,
<0xab 183>,
<0xb7 388>,
<0xe8 388>,
<0xf8 184>,
<0xaf 185>,
<0xed KEY_VOLUMEDOWN>,
<0xee 186>,
<0xb3 KEY_VOLUMEDOWN>,
<0xf1 KEY_VOLUMEDOWN>,
<0xf2 KEY_VOLUMEDOWN>,
<0xf3 KEY_SEARCH>,
<0xb4 KEY_VOLUMEDOWN>,
<0xa4 KEY_SETUP>,
<0xbe KEY_SEARCH>;
};
ir_key3 {
rockchip,usercode = <0x1dcc>;
rockchip,key_table =
<0xee KEY_REPLY>,
<0xf0 KEY_BACK>,
<0xf8 KEY_UP>,
<0xbb KEY_DOWN>,
<0xef KEY_LEFT>,
<0xed KEY_RIGHT>,
<0xfc KEY_HOME>,
<0xf1 KEY_VOLUMEUP>,
<0xfd KEY_VOLUMEDOWN>,
<0xb7 KEY_SEARCH>,
<0xff KEY_POWER>,
<0xf3 KEY_MUTE>,
<0xbf KEY_MENU>,
<0xf9 0x191>,
<0xf5 0x192>,
<0xb3 388>,
<0xbe KEY_1>,
<0xba KEY_2>,
<0xb2 KEY_3>,
<0xbd KEY_4>,
<0xf9 KEY_5>,
<0xb1 KEY_6>,
<0xfc KEY_7>,
<0xf8 KEY_8>,
<0xb0 KEY_9>,
<0xb6 KEY_0>,
<0xb5 KEY_BACKSPACE>;
};
};
&sdio {
status = "okay";
mmc-pwrseq = <&sdio_pwrseq>;
};
&sdmmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr &sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
};
&spdif {
status = "okay";
#sound-dai-cells = <0>;
};
&threshold {
temperature = <90000>; /* millicelsius */
};
&target {
temperature = <105000>; /* millicelsius */
};
&soc_crit {
temperature = <110000>; /* millicelsius */
};
&tsadc {
rockchip,hw-tshut-temp = <120000>;
status = "okay";
};
&u2phy0_host {
phy-supply = <&vcc_host>;
};
&u2phy1_host {
phy-supply = <&vcc_host>;
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host2_ehci {
status = "okay";
};
&usb_host2_ohci {
status = "okay";
};

23
arch/arm/boot/dts/rk3229-evb.dts
View File

@@ -84,6 +84,19 @@
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,rk3229";
simple-audio-card,cpu {
sound-dai = <&i2s1>;
};
simple-audio-card,codec {
sound-dai = <&codec>;
};
};
hdmi_sound: hdmi-sound {
status = "okay";
compatible = "simple-audio-card";
@@ -266,6 +279,16 @@
#sound-dai-cells = <0>;
};
&i2s1 {
#sound-dai-cells = <0>;
status = "okay";
};
&codec {
#sound-dai-cells = <0>;
status = "okay";
};
&pinctrl {
keys {
pwr_key: pwr-key {

47
arch/arm/boot/dts/rk322x-android.dtsi
View File

@@ -59,6 +59,53 @@
pinctrl-0 = <&uart21_xfer>;
};
firmware {
android {
compatible = "android,firmware";
fstab {
compatible = "android,fstab";
system {
compatible = "android,system";
dev = "/dev/block/by-name/system";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,verify";
};
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,verify";
};
};
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
};
ramoops_mem: ramoops@62e00000 {
reg = <0x62e00000 0xf0000>;
};
};
ramoops {
compatible = "ramoops";
record-size = <0x0 0x20000>;
console-size = <0x0 0x80000>;
ftrace-size = <0x0 0x00000>;
pmsg-size = <0x0 0x50000>;
memory-region = <&ramoops_mem>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";

35
arch/arm/boot/dts/rk322x-dram-default-timing.dtsi Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/clock/rockchip-ddr.h>
#include <dt-bindings/dram/rockchip,rk322x.h>
/ {
dram_timing: dram_timing {
compatible = "rockchip,dram-timing";
dram_spd_bin = <DDR3_DEFAULT>;
sr_idle = <0x18>;
pd_idle = <0x20>;
dram_dll_disb_freq = <300>;
phy_dll_disb_freq = <400>;
dram_odt_disb_freq = <333>;
phy_odt_disb_freq = <333>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
lpddr3_drv = <LP3_DS_34ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
lpddr2_drv = <LP2_DS_34ohm>;
/* lpddr2 not supported odt */
phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_45ohm>;
phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_45ohm>;
phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_34ohm>;
phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
phy_lp23_clk_drv = <PHY_LP23_RON_RTT_43ohm>;
phy_lp23_cmd_drv = <PHY_LP23_RON_RTT_34ohm>;
phy_lp23_dqs_drv = <PHY_LP23_RON_RTT_34ohm>;
phy_lp3_odt = <PHY_LP23_RON_RTT_240ohm>;
};
};

85
arch/arm/boot/dts/rk322x.dtsi
View File

@@ -47,6 +47,8 @@
#include <dt-bindings/suspend/rockchip-rk322x.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <rk322x-dram-default-timing.dtsi>
#include "skeleton.dtsi"
/ {
@@ -158,9 +160,62 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
dmc: dmc {
compatible = "rockchip,rk3228-dmc", "rockchip,rk322x-dram";
clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 600000
SYS_STATUS_VIDEO_4K 600000
SYS_STATUS_VIDEO_4K_10B 786000
>;
dram_freq = <786000000>;
rockchip,dram_timing = <&dram_timing>;
#cooling-cells = <2>;
status = "disabled";
ddr_power_model: ddr_power_model {
compatible = "ddr_power_model";
dynamic-power-coefficient = <120>;
static-power-coefficient = <200>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "soc-thermal";
};
};
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1050000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1050000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1050000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <1100000>;
};
opp-786000000 {
opp-hz = /bits/ 64 <786000000>;
opp-microvolt = <1150000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1150000>;
};
};
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -231,7 +286,7 @@
};
grf: syscon@11000000 {
compatible = "syscon", "simple-mfd";
compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
reg = <0x11000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -494,7 +549,8 @@
pwm3: pwm@110b0030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0030 0x10>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
@@ -569,6 +625,12 @@
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map2 {
trip = <&target>;
cooling-device =
<&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
};
@@ -592,6 +654,15 @@
status = "disabled";
};
codec: codec@12010000 {
compatible = "rockchip,rk3228-codec";
reg = <0x12010000 0x1000>;
clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
clock-names = "mclk", "pclk", "sclk";
spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
hdmi_phy: hdmi-phy@12030000 {
compatible = "rockchip,rk3228-hdmi-phy";
reg = <0x12030000 0x10000>;
@@ -785,7 +856,7 @@
status = "disabled";
};
display-subsystem {
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
};
@@ -972,17 +1043,17 @@
qos_vpu: qos@31040000 {
compatible = "syscon";
reg = <0x0 0x31040000 0x0 0x20>;
reg = <0x31040000 0x20>;
};
qos_rkvdec_r: qos@31070000 {
compatible = "syscon";
reg = <0x0 0x31070000 0x0 0x20>;
reg = <0x31070000 0x20>;
};
qos_rkvdec_w: qos@31070080 {
compatible = "syscon";
reg = <0x0 0x31070080 0x0 0x20>;
reg = <0x31070080 0x20>;
};
gic: interrupt-controller@32010000 {

9
arch/arm/boot/dts/rk3288-android.dtsi
View File

@@ -231,6 +231,15 @@
charge_logo,mode = "center";
connect = <&vopl_out_lvds>;
};
route_hdmi: route-hdmi {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vopb_out_hdmi>;
};
};
};

1
arch/arm/boot/dts/rk3288-box.dts
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3288.dtsi"

1
arch/arm/boot/dts/rk3288-chrome.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3288.dtsi"

1
arch/arm/boot/dts/rk3288-cif-sensor.dtsi Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3288.dtsi"
#include "rk3288-pinctrl.dtsi"
#include "../../mach-rockchip/rk_camera_sensor_info.h"

15
arch/arm/boot/dts/rk3288-evb-android-rk808-edp.dts
View File

@@ -68,14 +68,14 @@
/delete-node/ sdmmc-regulator;
vdd_log: vdd-center {
vdd_log: vdd-logic {
compatible = "pwm-regulator";
rockchip,pwm_id = <1>;
rockchip,pwm_voltage = <1100000>;
pwms = <&pwm1 0 25000 1>;
regulator-name = "vcc_log";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-min-microvolt = <860000>;
regulator-max-microvolt = <1360000>;
regulator-always-on;
regulator-boot-on;
};
@@ -144,6 +144,10 @@
mali-supply = <&vdd_gpu>;
};
&gmac {
max-speed = <1000>;
};
&hdmi_analog_sound {
status = "okay";
};
@@ -407,6 +411,11 @@
&rockchip_suspend {
status = "okay";
rockchip,pwm-regulator-config = <
(0
| PWM1_REGULATOR_EN
)
>;
};
&pwm1 {

1
arch/arm/boot/dts/rk3288-fpga.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/clock/ddr.h>

1
arch/arm/boot/dts/rk3288-p977.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3288.dtsi"

1
arch/arm/boot/dts/rk3288-p977_8846.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3288.dtsi"

1
arch/arm/boot/dts/rk3288-pinctrl.dtsi Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>

2
arch/arm/boot/dts/rk3288-popmetal-android-vga.dts
View File

@@ -262,6 +262,8 @@
};
&lvds {
pinctrl-names = "default";
pinctrl-0 = <&lcdc_ctl>;
status = "okay";
ports {

2
arch/arm/boot/dts/rk3288-popmetal-android.dts
View File

@@ -223,6 +223,8 @@
};
&lvds {
pinctrl-names = "default";
pinctrl-0 = <&lcdc_ctl>;
status = "okay";
};

1
arch/arm/boot/dts/rk3288-tb.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3288.dtsi"

1
arch/arm/boot/dts/rk3288-tb_8846.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3288.dtsi"

1
arch/arm/boot/dts/rk3288-tb_sec.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3288-tb_8846.dts"

1
arch/arm/boot/dts/rk3288-tesco.dts Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3288.dtsi"

11
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -1452,6 +1452,15 @@
};
};
mipi_phy_tx1rx1: mipi-phy-tx1rx1@ff968000 {
compatible = "rockchip,rk3288-mipi-dphy";
reg = <0x0 0xff968000 0x0 0x4000>;
rockchip,grf = <&grf>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
clock-names = "dphy-ref", "pclk";
status = "disabled";
};
edp: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0x0 0xff970000 0x0 0x4000>;
@@ -1490,8 +1499,6 @@
reg = <0x0 0xff96c000 0x0 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>;
clock-names = "pclk_lvds";
pinctrl-names = "lcdc";
pinctrl-0 = <&lcdc_ctl>;
power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";

1
arch/arm/boot/dts/rk616.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
&rk616 {

1
arch/arm/boot/dts/rk808.dtsi Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
&rk808 {
compatible = "rockchip,rk808";

1
arch/arm/boot/dts/rk818.dtsi Executable file → Normal file
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
&rk818 {
compatible = "rockchip,rk818";

1
arch/arm/boot/dts/vtl_ts_p977.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/{
tp-fw{

1
arch/arm/boot/dts/vtl_ts_sdk8846.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/{
tp-fw{

13
arch/arm/configs/rockchip_defconfig
View File

@@ -8,12 +8,15 @@ CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_NAMESPACES=y
@@ -27,7 +30,6 @@ CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_LZ4 is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
@@ -73,7 +75,6 @@ CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# CONFIG_COREDUMP is not set
CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -151,7 +152,6 @@ CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
@@ -226,6 +226,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_ROCKCHIP_SCR=y
CONFIG_SRAM=y
CONFIG_UID_SYS_STATS=y
CONFIG_MEMORY_STATE_TIME=y
CONFIG_USB_CAM_GPIO=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
@@ -466,6 +467,7 @@ CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_ES8316=y
CONFIG_SND_SOC_GVA_CODEC=y
CONFIG_SND_SOC_RK312X=y
CONFIG_SND_SOC_RK3228=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_RT5651=y
CONFIG_SND_SOC_SPDIF=y
@@ -563,7 +565,6 @@ CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_OPTION=y
CONFIG_USB_TRANCEVIBRATOR=y
CONFIG_USB_OTG_WAKELOCK=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_GADGET_VBUS_DRAW=500
@@ -599,7 +600,6 @@ CONFIG_STAGING=y
CONFIG_INV_MPU_IIO=y
CONFIG_ASHMEM=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
CONFIG_SYNC=y
CONFIG_SW_SYNC=y
CONFIG_SW_SYNC_USER=y
@@ -613,6 +613,7 @@ CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_ANDROID_VERSION=0x08000000
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_PVTM=y
CONFIG_ROCKCHIP_SUSPEND_MODE=y

1
arch/arm/mach-rockchip/embedded/Makefile
View File

@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for embedded code blobs for Rockchip SoCs
#
# These code blobs are emedded into vmlinux and copied into SRAM

1
arch/arm/mach-rockchip/embedded/rk3288_resume.lds.S
View File

@@ -1,3 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
MEMORY {
pmu_sram_code : ORIGIN = 0xff720000, LENGTH = 0xf00
pmu_sram_stack : ORIGIN = 0xff720f00, LENGTH = 0x100

2
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -1,10 +1,12 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-lvds-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3366-fpga.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3366-sheep.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb

22
arch/arm64/boot/dts/rockchip/px30-android.dtsi
View File

@@ -6,7 +6,7 @@
/ {
chosen {
bootargs = "earlyprintk=uart8250,mmio32,0xff160000 swiotlb=1";
bootargs = "earlyprintk=uart8250,mmio32,0xff160000 swiotlb=1 console=ttyFIQ0 androidboot.baseband=N/A androidboot.selinux=permissive androidboot.veritymode=/dev/block/by-name/metadata androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init";
};
fiq-debugger {
@@ -17,6 +17,8 @@
rockchip,irq-mode-enable = <0>;
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
@@ -27,14 +29,14 @@
compatible = "android,fstab";
system {
compatible = "android,system";
dev = "/dev/block/platform/ff390000.dwmmc/by-name/system";
dev = "/dev/block/by-name/system";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,verify";
};
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/ff390000.dwmmc/by-name/vendor";
dev = "/dev/block/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,verify";
@@ -53,6 +55,20 @@
reg = <0x0 0x0 0x0 0x0>;
};
};
ramoops_mem: ramoops_mem {
reg = <0x0 0x110000 0x0 0xf0000>;
reg-names = "ramoops_mem";
};
ramoops {
compatible = "ramoops";
record-size = <0x0 0x20000>;
console-size = <0x0 0x80000>;
ftrace-size = <0x0 0x00000>;
pmsg-size = <0x0 0x50000>;
memory-region = <&ramoops_mem>;
};
};
&display_subsystem {

294
arch/arm64/boot/dts/rockchip/px30-dram-default-timing.dtsi Normal file
View File

@@ -0,0 +1,294 @@
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/clock/rockchip-ddr.h>
#include <dt-bindings/memory/px30-dram.h>
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr2_speed_bin = <DDR2_DEFAULT>;
ddr3_speed_bin = <DDR3_DEFAULT>;
ddr4_speed_bin = <DDR4_DEFAULT>;
pd_idle = <0>;
sr_idle = <0>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
auto_pd_dis_freq = <1066>;
auto_sr_dis_freq = <800>;
ddr2_dll_dis_freq = <300>;
ddr3_dll_dis_freq = <300>;
ddr4_dll_dis_freq = <625>;
phy_dll_dis_freq = <400>;
ddr2_odt_dis_freq = <100>;
phy_ddr2_odt_dis_freq = <100>;
ddr2_drv = <DDR2_DS_REDUCE>;
ddr2_odt = <DDR2_ODT_150ohm>;
phy_ddr2_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
phy_ddr2_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
phy_ddr2_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
phy_ddr2_odt = <PHY_DDR3_RON_RTT_225ohm>;
ddr3_odt_dis_freq = <100>;
phy_ddr3_odt_dis_freq = <100>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
phy_lpddr2_odt_dis_freq = <666>;
lpddr2_drv = <LP2_DS_40ohm>;
phy_lpddr2_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
phy_lpddr2_ck_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_43ohm>;
phy_lpddr2_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
phy_lpddr2_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_DISABLE>;
lpddr3_odt_dis_freq = <666>;
phy_lpddr3_odt_dis_freq = <666>;
lpddr3_drv = <LP3_DS_40ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_43ohm>;
phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
phy_lpddr3_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_240ohm>;
lpddr4_odt_dis_freq = <800>;
phy_lpddr4_odt_dis_freq = <800>;
lpddr4_drv = <LP4_PDDS_60ohm>;
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_40ohm>;
phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_80ohm>;
phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_80ohm>;
phy_lpddr4_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_60ohm>;
ddr4_odt_dis_freq = <666>;
phy_ddr4_odt_dis_freq = <666>;
ddr4_drv = <DDR4_DS_34ohm>;
ddr4_odt = <DDR4_RTT_NOM_240ohm>;
phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_43ohm>;
phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
phy_ddr4_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_240ohm>;
/* CA de-skew, one step is 47.8ps, range 0-15 */
ddr3a1_ddr4a9_de-skew = <7>;
ddr3a0_ddr4a10_de-skew = <7>;
ddr3a3_ddr4a6_de-skew = <8>;
ddr3a2_ddr4a4_de-skew = <8>;
ddr3a5_ddr4a8_de-skew = <7>;
ddr3a4_ddr4a5_de-skew = <9>;
ddr3a7_ddr4a11_de-skew = <7>;
ddr3a6_ddr4a7_de-skew = <9>;
ddr3a9_ddr4a0_de-skew = <8>;
ddr3a8_ddr4a13_de-skew = <7>;
ddr3a11_ddr4a3_de-skew = <9>;
ddr3a10_ddr4cs0_de-skew = <7>;
ddr3a13_ddr4a2_de-skew = <8>;
ddr3a12_ddr4ba1_de-skew = <7>;
ddr3a15_ddr4odt0_de-skew = <7>;
ddr3a14_ddr4a1_de-skew = <8>;
ddr3ba1_ddr4a15_de-skew = <7>;
ddr3ba0_ddr4bg0_de-skew = <7>;
ddr3ras_ddr4cke_de-skew = <7>;
ddr3ba2_ddr4ba0_de-skew = <8>;
ddr3we_ddr4bg1_de-skew = <8>;
ddr3cas_ddr4a12_de-skew = <7>;
ddr3ckn_ddr4ckn_de-skew = <8>;
ddr3ckp_ddr4ckp_de-skew = <8>;
ddr3cke_ddr4a16_de-skew = <8>;
ddr3odt0_ddr4a14_de-skew = <7>;
ddr3cs0_ddr4act_de-skew = <8>;
ddr3reset_ddr4reset_de-skew = <7>;
ddr3cs1_ddr4cs1_de-skew = <7>;
ddr3odt1_ddr4odt1_de-skew = <7>;
/* DATA de-skew
* RX one step is 25.1ps, range 0-15
* TX one step is 47.8ps, range 0-15
*/
cs0_dm0_rx_de-skew = <7>;
cs0_dm0_tx_de-skew = <8>;
cs0_dq0_rx_de-skew = <7>;
cs0_dq0_tx_de-skew = <8>;
cs0_dq1_rx_de-skew = <7>;
cs0_dq1_tx_de-skew = <8>;
cs0_dq2_rx_de-skew = <7>;
cs0_dq2_tx_de-skew = <8>;
cs0_dq3_rx_de-skew = <7>;
cs0_dq3_tx_de-skew = <8>;
cs0_dq4_rx_de-skew = <7>;
cs0_dq4_tx_de-skew = <8>;
cs0_dq5_rx_de-skew = <7>;
cs0_dq5_tx_de-skew = <8>;
cs0_dq6_rx_de-skew = <7>;
cs0_dq6_tx_de-skew = <8>;
cs0_dq7_rx_de-skew = <7>;
cs0_dq7_tx_de-skew = <8>;
cs0_dqs0_rx_de-skew = <6>;
cs0_dqs0p_tx_de-skew = <9>;
cs0_dqs0n_tx_de-skew = <9>;
cs0_dm1_rx_de-skew = <7>;
cs0_dm1_tx_de-skew = <7>;
cs0_dq8_rx_de-skew = <7>;
cs0_dq8_tx_de-skew = <8>;
cs0_dq9_rx_de-skew = <7>;
cs0_dq9_tx_de-skew = <7>;
cs0_dq10_rx_de-skew = <7>;
cs0_dq10_tx_de-skew = <8>;
cs0_dq11_rx_de-skew = <7>;
cs0_dq11_tx_de-skew = <7>;
cs0_dq12_rx_de-skew = <7>;
cs0_dq12_tx_de-skew = <8>;
cs0_dq13_rx_de-skew = <7>;
cs0_dq13_tx_de-skew = <7>;
cs0_dq14_rx_de-skew = <7>;
cs0_dq14_tx_de-skew = <8>;
cs0_dq15_rx_de-skew = <7>;
cs0_dq15_tx_de-skew = <7>;
cs0_dqs1_rx_de-skew = <7>;
cs0_dqs1p_tx_de-skew = <9>;
cs0_dqs1n_tx_de-skew = <9>;
cs0_dm2_rx_de-skew = <7>;
cs0_dm2_tx_de-skew = <8>;
cs0_dq16_rx_de-skew = <7>;
cs0_dq16_tx_de-skew = <8>;
cs0_dq17_rx_de-skew = <7>;
cs0_dq17_tx_de-skew = <8>;
cs0_dq18_rx_de-skew = <7>;
cs0_dq18_tx_de-skew = <8>;
cs0_dq19_rx_de-skew = <7>;
cs0_dq19_tx_de-skew = <8>;
cs0_dq20_rx_de-skew = <7>;
cs0_dq20_tx_de-skew = <8>;
cs0_dq21_rx_de-skew = <7>;
cs0_dq21_tx_de-skew = <8>;
cs0_dq22_rx_de-skew = <7>;
cs0_dq22_tx_de-skew = <8>;
cs0_dq23_rx_de-skew = <7>;
cs0_dq23_tx_de-skew = <8>;
cs0_dqs2_rx_de-skew = <6>;
cs0_dqs2p_tx_de-skew = <9>;
cs0_dqs2n_tx_de-skew = <9>;
cs0_dm3_rx_de-skew = <7>;
cs0_dm3_tx_de-skew = <7>;
cs0_dq24_rx_de-skew = <7>;
cs0_dq24_tx_de-skew = <8>;
cs0_dq25_rx_de-skew = <7>;
cs0_dq25_tx_de-skew = <7>;
cs0_dq26_rx_de-skew = <7>;
cs0_dq26_tx_de-skew = <7>;
cs0_dq27_rx_de-skew = <7>;
cs0_dq27_tx_de-skew = <7>;
cs0_dq28_rx_de-skew = <7>;
cs0_dq28_tx_de-skew = <7>;
cs0_dq29_rx_de-skew = <7>;
cs0_dq29_tx_de-skew = <7>;
cs0_dq30_rx_de-skew = <7>;
cs0_dq30_tx_de-skew = <7>;
cs0_dq31_rx_de-skew = <7>;
cs0_dq31_tx_de-skew = <7>;
cs0_dqs3_rx_de-skew = <7>;
cs0_dqs3p_tx_de-skew = <9>;
cs0_dqs3n_tx_de-skew = <9>;
cs1_dm0_rx_de-skew = <7>;
cs1_dm0_tx_de-skew = <8>;
cs1_dq0_rx_de-skew = <7>;
cs1_dq0_tx_de-skew = <8>;
cs1_dq1_rx_de-skew = <7>;
cs1_dq1_tx_de-skew = <8>;
cs1_dq2_rx_de-skew = <7>;
cs1_dq2_tx_de-skew = <8>;
cs1_dq3_rx_de-skew = <7>;
cs1_dq3_tx_de-skew = <8>;
cs1_dq4_rx_de-skew = <7>;
cs1_dq4_tx_de-skew = <8>;
cs1_dq5_rx_de-skew = <7>;
cs1_dq5_tx_de-skew = <8>;
cs1_dq6_rx_de-skew = <7>;
cs1_dq6_tx_de-skew = <8>;
cs1_dq7_rx_de-skew = <7>;
cs1_dq7_tx_de-skew = <8>;
cs1_dqs0_rx_de-skew = <6>;
cs1_dqs0p_tx_de-skew = <9>;
cs1_dqs0n_tx_de-skew = <9>;
cs1_dm1_rx_de-skew = <7>;
cs1_dm1_tx_de-skew = <7>;
cs1_dq8_rx_de-skew = <7>;
cs1_dq8_tx_de-skew = <8>;
cs1_dq9_rx_de-skew = <7>;
cs1_dq9_tx_de-skew = <7>;
cs1_dq10_rx_de-skew = <7>;
cs1_dq10_tx_de-skew = <8>;
cs1_dq11_rx_de-skew = <7>;
cs1_dq11_tx_de-skew = <7>;
cs1_dq12_rx_de-skew = <7>;
cs1_dq12_tx_de-skew = <8>;
cs1_dq13_rx_de-skew = <7>;
cs1_dq13_tx_de-skew = <7>;
cs1_dq14_rx_de-skew = <7>;
cs1_dq14_tx_de-skew = <8>;
cs1_dq15_rx_de-skew = <7>;
cs1_dq15_tx_de-skew = <7>;
cs1_dqs1_rx_de-skew = <7>;
cs1_dqs1p_tx_de-skew = <9>;
cs1_dqs1n_tx_de-skew = <9>;
cs1_dm2_rx_de-skew = <7>;
cs1_dm2_tx_de-skew = <8>;
cs1_dq16_rx_de-skew = <7>;
cs1_dq16_tx_de-skew = <8>;
cs1_dq17_rx_de-skew = <7>;
cs1_dq17_tx_de-skew = <8>;
cs1_dq18_rx_de-skew = <7>;
cs1_dq18_tx_de-skew = <8>;
cs1_dq19_rx_de-skew = <7>;
cs1_dq19_tx_de-skew = <8>;
cs1_dq20_rx_de-skew = <7>;
cs1_dq20_tx_de-skew = <8>;
cs1_dq21_rx_de-skew = <7>;
cs1_dq21_tx_de-skew = <8>;
cs1_dq22_rx_de-skew = <7>;
cs1_dq22_tx_de-skew = <8>;
cs1_dq23_rx_de-skew = <7>;
cs1_dq23_tx_de-skew = <8>;
cs1_dqs2_rx_de-skew = <6>;
cs1_dqs2p_tx_de-skew = <9>;
cs1_dqs2n_tx_de-skew = <9>;
cs1_dm3_rx_de-skew = <7>;
cs1_dm3_tx_de-skew = <7>;
cs1_dq24_rx_de-skew = <7>;
cs1_dq24_tx_de-skew = <8>;
cs1_dq25_rx_de-skew = <7>;
cs1_dq25_tx_de-skew = <7>;
cs1_dq26_rx_de-skew = <7>;
cs1_dq26_tx_de-skew = <7>;
cs1_dq27_rx_de-skew = <7>;
cs1_dq27_tx_de-skew = <7>;
cs1_dq28_rx_de-skew = <7>;
cs1_dq28_tx_de-skew = <7>;
cs1_dq29_rx_de-skew = <7>;
cs1_dq29_tx_de-skew = <7>;
cs1_dq30_rx_de-skew = <7>;
cs1_dq30_tx_de-skew = <7>;
cs1_dq31_rx_de-skew = <7>;
cs1_dq31_tx_de-skew = <7>;
cs1_dqs3_rx_de-skew = <7>;
cs1_dqs3p_tx_de-skew = <9>;
cs1_dqs3n_tx_de-skew = <9>;
};
};

626
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-lvds-v10.dts Normal file
View File

@@ -0,0 +1,626 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/sensor-dev.h>
#include "px30.dtsi"
#include "px30-android.dtsi"
/ {
model = "Rockchip PX30 evb ddr3 lvds board";
compatible = "rockchip,px30-evb-ddr3-lvds-v10", "rockchip,px30";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 2>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
esc-key {
linux,code = <KEY_ESC>;
label = "esc";
press-threshold-microvolt = <1270000>;
};
home-key {
linux,code = <KEY_HOME>;
label = "home";
press-threshold-microvolt = <602000>;
};
menu-key {
linux,code = <KEY_MENU>;
label = "menu";
press-threshold-microvolt = <952000>;
};
vol-down-key {
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <290000>;
};
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <17000>;
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 25000 0>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
};
panel {
compatible = "samsung,lsl070nl01", "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
width-mm = <217>;
height-mm = <136>;
rockchip,data-mapping = "vesa";
rockchip,data-width = <24>;
rockchip,output = "lvds";
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <49500000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <90>;
hfront-porch = <90>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <90>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
/*clocks = <&rk809 1>;*/
/*clock-names = "ext_clock";*/
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
vcc5v0_sys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
wireless-wlan {
compatible = "wlan-platdata";
wifi_chip_type = "AP6210";
WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless-bluetooth {
compatible = "bluetooth-platdata";
/*clocks = <&rk809 1>;*/
/*clock-names = "ext_clock";*/
uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default","rts_gpio";
pinctrl-0 = <&uart1_rts>;
pinctrl-1 = <&uart1_rts_gpio>;
BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&display_subsystem {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
supports-emmc;
disable-wp;
non-removable;
num-slots = <1>;
status = "okay";
};
&gmac {
phy-supply = <&vcc_phy>;
clock_in_out = "output";
snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_logic>;
status = "okay";
};
&i2c0 {
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-initial-mode = <0x1>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc2v5_ddr: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5_ddr";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v0_soc: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc1v0_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_dvp: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v5_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd1v5_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcc3v3_sys: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_sys";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc3v3_lcd: SWITCH_REG1 {
regulator-boot-on;
regulator-name = "vcc3v3_lcd";
};
vcc5v0_host: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc5v0_host";
};
};
};
};
&i2c1 {
status = "okay";
sensor@0f {
status = "okay";
compatible = "ak8963";
reg = <0x0f>;
type = <SENSOR_TYPE_COMPASS>;
irq_enable = <0>;
poll_delay_ms = <30>;
layout = <1>;
reprobe_en = <1>;
};
gt1x: gt1x@14 {
compatible = "goodix,gt1x";
reg = <0x14>;
goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
};
sensor@4c {
status = "okay";
compatible = "gs_mma7660";
reg = <0x4c>;
type = <SENSOR_TYPE_ACCEL>;
irq-gpio = <&gpio0 RK_PB7 IRQ_TYPE_LEVEL_LOW>;
irq_enable = <0>;
poll_delay_ms = <30>;
layout = <2>;
reprobe_en = <1>;
};
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc1v8_soc>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_3v0>;
vccio4-supply = <&vcc3v0_pmu>;
vccio5-supply = <&vcc_3v0>;
};
&lvds {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&lvds_in_vopl {
status = "disabled";
};
&route_lvds {
status = "okay";
};
&nandc0 {
status = "okay";
};
&pinctrl {
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v0_pmu>;
pmuio2-supply = <&vcc3v0_pmu>;
};
&pwm1 {
status = "okay";
};
&rk_rga {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc1v8_soc>;
};
&sdmmc {
cap-mmc-highspeed;
supports-sd;
broken-cd;
card-detect-delay = <800>;
ignore-pm-notify;
keep-power-in-suspend;
/*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/
status = "disabled";
};
&sdio {
max-frequency = <50000000>;
cap-sd-highspeed;
supports-sdio;
ignore-pm-notify;
keep-power-in-suspend;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
status = "okay";
};
&tsadc {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "okay";
};
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&vpu_combo {
status = "okay";
};

410
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts
View File

@@ -21,36 +21,37 @@
compatible = "adc-keys";
io-channels = <&saradc 2>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <10000>;
};
vol-down-key {
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <170000>;
esc-key {
linux,code = <KEY_ESC>;
label = "esc";
press-threshold-microvolt = <1310000>;
};
home-key {
linux,code = <KEY_HOME>;
label = "home";
press-threshold-microvolt = <254000>;
press-threshold-microvolt = <624000>;
};
menu-key {
linux,code = <KEY_MENU>;
label = "menu";
press-threshold-microvolt = <414000>;
press-threshold-microvolt = <987000>;
};
esc-key {
linux,code = <KEY_ESC>;
label = "esc";
press-threshold-microvolt = <614000>;
vol-down-key {
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <300000>;
};
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <17000>;
};
};
@@ -93,6 +94,35 @@
default-brightness-level = <200>;
};
rk809-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rk809-codec";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Mic Jack", "MICBIAS1",
"IN1P", "Mic Jack",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
simple-audio-card,cpu {
sound-dai = <&i2s1_2ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809_codec>;
};
};
rk_headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
io-channels = <&saradc 1>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
/*clocks = <&rk809 1>;*/
@@ -116,6 +146,15 @@
regulator-boot-on;
};
vcc5v0_sys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
wireless-wlan {
compatible = "wlan-platdata";
wifi_chip_type = "AP6210";
@@ -148,7 +187,7 @@
panel@0 {
compatible = "sitronix,st7703", "simple-panel-dsi";
reg = <0>;
//power-supply = <&vcc3v3_lcd>;
power-supply = <&vcc3v3_lcd>;
backlight = <&backlight>;
prepare-delay-ms = <2>;
reset-delay-ms = <1>;
@@ -235,6 +274,10 @@
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&dsi_in_vopl {
status = "disabled";
};
@@ -247,14 +290,14 @@
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gmac {
phy-supply = <&vcc_phy>;
clock_in_out = "output";
assigned-clocks = <&cru SCLK_GMAC>;
assigned-clock-parents = <&gmac_clkin>;
clock_in_out = "input";
snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
@@ -262,9 +305,247 @@
};
&gpu {
mali-supply = <&vdd_logic>;
status = "okay";
};
&i2c0 {
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
pwrkey {
status = "okay";
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-initial-mode = <0x1>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc2v5_ddr: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5_ddr";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v0_soc: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc1v0_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_dvp: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v5_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd1v5_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcc3v3_sys: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_sys";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc3v3_lcd: SWITCH_REG1 {
regulator-boot-on;
regulator-name = "vcc3v3_lcd";
};
vcc5v0_host: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc5v0_host";
};
};
rk809_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
hp-volume = <20>;
spk-volume = <3>;
status = "okay";
};
};
};
&i2c1 {
status = "okay";
@@ -279,12 +560,11 @@
reprobe_en = <1>;
};
ts@40 {
status = "okay";
compatible = "GT1X";
reg = <0x14>;
irq_gpio_number = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
rst_gpio_number = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
gt1x: gt1x@14 {
compatible = "goodix,gt1x";
reg = <0x14>;
goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
};
sensor@4c {
@@ -295,16 +575,48 @@
irq-gpio = <&gpio0 RK_PB7 IRQ_TYPE_LEVEL_LOW>;
irq_enable = <0>;
poll_delay_ms = <30>;
layout = <6>;
layout = <2>;
reprobe_en = <1>;
};
};
&i2s1_2ch {
status = "okay";
#sound-dai-cells = <0>;
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc1v8_soc>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_3v0>;
vccio4-supply = <&vcc3v0_pmu>;
vccio5-supply = <&vcc_3v0>;
};
&mipi_dphy {
status = "okay";
};
&nandc0 {
status = "okay";
};
&pinctrl {
headphone {
hp_det: hp-det {
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -312,16 +624,28 @@
};
};
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v0_pmu>;
pmuio2-supply = <&vcc3v0_pmu>;
};
&pwm1 {
status = "okay";
};
&rk_rga {
status = "okay";
};
&route_dsi {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc1v8_soc>;
};
&sdmmc {
@@ -346,12 +670,40 @@
status = "okay";
};
&tsadc {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "okay";
};
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&vopb {
status = "okay";
};
@@ -367,3 +719,7 @@
&vopl_mmu {
status = "okay";
};
&vpu_combo {
status = "okay";
};

429
arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts
View File

@@ -21,36 +21,37 @@
compatible = "adc-keys";
io-channels = <&saradc 2>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
esc-key {
linux,code = <KEY_ESC>;
label = "esc";
press-threshold-microvolt = <614000>;
press-threshold-microvolt = <1310000>;
};
home-key {
linux,code = <KEY_HOME>;
label = "home";
press-threshold-microvolt = <254000>;
press-threshold-microvolt = <624000>;
};
menu-key {
linux,code = <KEY_MENU>;
label = "menu";
press-threshold-microvolt = <414000>;
};
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <10000>;
press-threshold-microvolt = <987000>;
};
vol-down-key {
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <170000>;
press-threshold-microvolt = <300000>;
};
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <17000>;
};
};
@@ -93,6 +94,35 @@
default-brightness-level = <200>;
};
rk809-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rk809-codec";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Mic Jack", "MICBIAS1",
"IN1P", "Mic Jack",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
simple-audio-card,cpu {
sound-dai = <&i2s1_2ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809_codec>;
};
};
rk_headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
io-channels = <&saradc 1>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
/*clocks = <&rk809 1>;*/
@@ -116,6 +146,15 @@
regulator-boot-on;
};
vcc5v0_sys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
wireless-wlan {
compatible = "wlan-platdata";
wifi_chip_type = "AP6210";
@@ -148,7 +187,7 @@
panel@0 {
compatible = "sitronix,st7703", "simple-panel-dsi";
reg = <0>;
//power-supply = <&vcc3v3_lcd>;
power-supply = <&vcc3v3_lcd>;
backlight = <&backlight>;
prepare-delay-ms = <2>;
reset-delay-ms = <1>;
@@ -235,30 +274,8 @@
};
};
&i2c1 {
status = "okay";
sensor@0f {
status = "okay";
compatible = "ak8963";
reg = <0x0f>;
type = <SENSOR_TYPE_COMPASS>;
irq_enable = <0>;
poll_delay_ms = <30>;
layout = <1>;
reprobe_en = <1>;
};
sensor@4c {
status = "okay";
compatible = "gs_mma7660";
reg = <0x4c>;
type = <SENSOR_TYPE_ACCEL>;
irq_enable = <0>;
poll_delay_ms = <30>;
layout = <6>;
reprobe_en = <1>;
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&dsi_in_vopl {
@@ -273,14 +290,14 @@
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gmac {
phy-supply = <&vcc_phy>;
clock_in_out = "output";
assigned-clocks = <&cru SCLK_GMAC>;
assigned-clock-parents = <&gmac_clkin>;
clock_in_out = "input";
snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
@@ -288,18 +305,267 @@
};
&gpu {
mali-supply = <&vdd_logic>;
status = "okay";
};
&i2c0 {
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
pwrkey {
status = "okay";
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc2v5_ddr: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-initial-mode = <0x1>;
regulator-name = "vcc2v5_ddr";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v0_soc: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc1v0_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_dvp: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v5_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd1v5_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcc3v3_sys: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_sys";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc3v3_lcd: SWITCH_REG1 {
regulator-boot-on;
regulator-name = "vcc3v3_lcd";
};
vcc5v0_host: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc5v0_host";
};
};
rk809_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
hp-volume = <20>;
spk-volume = <3>;
status = "okay";
};
};
};
&i2c1 {
status = "okay";
ts@40 {
sensor@0f {
status = "okay";
compatible = "GT1X";
reg = <0x14>;
irq_gpio_number = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
rst_gpio_number = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
compatible = "ak8963";
reg = <0x0f>;
type = <SENSOR_TYPE_COMPASS>;
irq_enable = <0>;
poll_delay_ms = <30>;
layout = <1>;
reprobe_en = <1>;
};
gt1x: gt1x@14 {
compatible = "goodix,gt1x";
reg = <0x14>;
goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
};
sensor@4c {
@@ -307,7 +573,6 @@
compatible = "gs_mma7660";
reg = <0x4c>;
type = <SENSOR_TYPE_ACCEL>;
irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
irq_enable = <0>;
poll_delay_ms = <30>;
layout = <6>;
@@ -315,11 +580,43 @@
};
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc1v8_soc>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_3v0>;
vccio4-supply = <&vcc3v0_pmu>;
vccio5-supply = <&vcc_3v0>;
};
&i2s1_2ch {
status = "okay";
#sound-dai-cells = <0>;
};
&mipi_dphy {
status = "okay";
};
&nandc0 {
status = "okay";
};
&pinctrl {
headphone {
hp_det: hp-det {
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -327,16 +624,28 @@
};
};
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v0_pmu>;
pmuio2-supply = <&vcc3v0_pmu>;
};
&pwm1 {
status = "okay";
};
&rk_rga {
status = "okay";
};
&route_dsi {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc1v8_soc>;
};
&sdmmc {
@@ -361,12 +670,40 @@
status = "okay";
};
&tsadc {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "okay";
};
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&vopb {
status = "okay";
};
@@ -382,3 +719,7 @@
&vopl_mmu {
status = "okay";
};
&vpu_combo {
status = "okay";
};

370
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@@ -12,6 +12,9 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/px30-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <dt-bindings/thermal/thermal.h>
#include "px30-dram-default-timing.dtsi"
/ {
compatible = "rockchip,px30";
@@ -24,6 +27,9 @@
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -40,6 +46,8 @@
compatible = "arm,cortex-a35", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu1: cpu@1 {
@@ -47,18 +55,59 @@
compatible = "arm,cortex-a35", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a35", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a35", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
};
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <1075000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1075000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1125000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1225000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1350000>;
clock-latency-ns = <40000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1425000>;
clock-latency-ns = <40000>;
status = "disabled";
};
};
@@ -84,6 +133,13 @@
};
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -104,6 +160,13 @@
clock-output-names = "xin24m";
};
xin32k: xin32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
pmu: power-management@ff000000 {
compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff000000 0x0 0x1000>;
@@ -113,7 +176,6 @@
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* These power domains are grouped by VD_LOGIC */
pd_usb@PX30_PD_USB {
@@ -186,7 +248,7 @@
};
pd_gpu@PX30_PD_GPU {
reg = <PX30_PD_GPU>;
clocks = <&cru ACLK_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
};
};
@@ -227,7 +289,7 @@
compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
reg = <0x0 0xff030000 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>;
clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
@@ -246,6 +308,19 @@
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 16>, <&dmac 17>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_8ch_sclktx
&i2s0_8ch_sclkrx
&i2s0_8ch_lrcktx
&i2s0_8ch_lrckrx
&i2s0_8ch_sdi0
&i2s0_8ch_sdi1
&i2s0_8ch_sdi2
&i2s0_8ch_sdi3
&i2s0_8ch_sdo0
&i2s0_8ch_sdo1
&i2s0_8ch_sdo2
&i2s0_8ch_sdo3>;
status = "disabled";
};
@@ -257,6 +332,11 @@
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 18>, <&dmac 19>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_sclk
&i2s1_2ch_lrck
&i2s1_2ch_sdi
&i2s1_2ch_sdo>;
status = "disabled";
};
@@ -268,6 +348,11 @@
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 20>, <&dmac 21>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s2_2ch_sclk
&i2s2_2ch_lrck
&i2s2_2ch_sdi
&i2s2_2ch_sdo>;
status = "disabled";
};
@@ -278,6 +363,13 @@
clock-names = "pdm_clk", "pdm_hclk";
dmas = <&dmac 24>;
dma-names = "rx";
pinctrl-names = "default";
pinctrl-0 = <&pdm_clk0m0
&pdm_clk1
&pdm_sdi0m0
&pdm_sdi1
&pdm_sdi2
&pdm_sdi3>;
status = "disabled";
};
@@ -325,7 +417,7 @@
reg = <0x0 0xff158000 0x0 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "sclk_uart", "pclk_uart";
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac 2>, <&dmac 3>;
@@ -475,7 +567,7 @@
#dma-cells = <2>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>;
pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
status = "disabled";
};
@@ -593,6 +685,23 @@
};
};
thermal_zones: thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
sustainable-power = <1000>; /* milliwatts */
thermal-sensors = <&tsadc 0>;
};
gpu_thermal: gpu-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 1>;
};
};
tsadc: tsadc@ff280000 {
compatible = "rockchip,px30-tsadc";
reg = <0x0 0xff280000 0x0 0x100>;
@@ -602,7 +711,7 @@
clock-names = "tsadc", "apb_pclk";
assigned-clocks = <&cru SCLK_TSADC>;
assigned-clock-rates = <50000>;
resets = <&cru SRST_TSADC_P>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&tsadc_otp_gpio>;
@@ -656,9 +765,9 @@
<&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>;
assigned-clock-rates =
<1200000000>, <100000000>,
<26000000>, <300000000>,
<300000000>, <150000000>,
<150000000>, <75000000>;
<26000000>, <200000000>,
<200000000>, <150000000>,
<150000000>, <100000000>;
};
usb2phy_grf: syscon@ff2c0000 {
@@ -672,7 +781,7 @@
compatible = "rockchip,px30-usb2phy",
"rockchip,rk3328-usb2phy";
reg = <0x100 0x10>;
clocks = <&cru SCLK_USBPHY_REF>;
clocks = <&pmucru SCLK_USBPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
assigned-clocks = <&cru USB480M>;
@@ -702,7 +811,7 @@
mipi_dphy: mipi-dphy@ff2e0000 {
compatible = "rockchip,px30-mipi-dphy";
reg = <0x0 0xff2e0000 0x0 0x10000>;
clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
clock-names = "ref", "pclk";
clock-output-names = "mipi_dphy_pll";
#clock-cells = <0>;
@@ -716,8 +825,7 @@
lvds: lvds@ff2e0000 {
compatible = "rockchip,px30-lvds";
reg = <0x0 0xff2e0000 0x0 0x100>, <0x0 0xff2e0100 0x0 0x100>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
reg = <0x0 0xff2e0000 0x0 0x10000>, <0x0 0xff450000 0x0 0x10000>;
clocks = <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";
power-domains = <&power PX30_PD_VO>;
@@ -733,14 +841,14 @@
#address-cells = <1>;
#size-cells = <0>;
lvds_in_vopl: endpoint@0 {
lvds_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopl_out_lvds>;
remote-endpoint = <&vopb_out_lvds>;
};
lvds_in_vopb: endpoint@1 {
lvds_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopb_out_lvds>;
remote-endpoint = <&vopl_out_lvds>;
};
};
};
@@ -753,6 +861,7 @@
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
power-domains = <&power PX30_PD_USB>;
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
@@ -767,9 +876,9 @@
compatible = "generic-ehci";
reg = <0x0 0xff340000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>,
<&u2phy>;
clocks = <&cru HCLK_HOST>, <&u2phy>;
clock-names = "usbhost", "arbiter", "utmi";
power-domains = <&power PX30_PD_USB>;
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -779,9 +888,9 @@
compatible = "generic-ohci";
reg = <0x0 0xff350000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>,
<&u2phy>;
clocks = <&cru HCLK_HOST>, <&u2phy>;
clock-names = "usbhost", "arbiter", "utmi";
power-domains = <&power PX30_PD_USB>;
phys = <&u2phy_host>;
phy-names = "usb";
};
@@ -815,8 +924,11 @@
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
power-domains = <&power PX30_PD_SDCARD>;
fifo-depth = <0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
status = "disabled";
};
@@ -827,8 +939,11 @@
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
power-domains = <&power PX30_PD_MMC_NAND>;
fifo-depth = <0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
status = "disabled";
};
@@ -839,6 +954,7 @@
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
power-domains = <&power PX30_PD_MMC_NAND>;
fifo-depth = <0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -851,6 +967,7 @@
nandc_id = <0>;
clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
clock-names = "clk_nandc", "hclk_nandc";
power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
@@ -863,12 +980,35 @@
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "GPU", "MMU", "JOB";
clocks = <&cru ACLK_GPU>;
clocks = <&cru SCLK_GPU>;
clock-names = "clk_mali";
power-domains = <&power PX30_PD_GPU>;
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
};
gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1025000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1075000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1225000>;
};
};
hevc: hevc_service@ff440000 {
compatible = "rockchip,hevc_sub";
iommu_enabled = <1>;
@@ -902,8 +1042,11 @@
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>,
<&cru SRST_IVPU_NIU_A>, <&cru SRST_VPU_NIU_H>;
reset-names = "video_a", "video_h", "niu_a", "niu_h";
<&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>,
<&cru SRST_VPU_CORE>;
reset-names = "video_a", "video_h", "niu_a", "niu_h",
"video_core";
power-domains = <&power PX30_PD_VPU>;
mode_bit = <15>;
mode_ctrl = <0x410>;
name = "vpu_combo";
@@ -917,6 +1060,7 @@
interrupt-names = "hevc_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "hclk";
power-domains = <&power PX30_PD_VPU>;
#iommu-cells = <0>;
};
@@ -927,6 +1071,7 @@
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "hclk";
power-domains = <&power PX30_PD_VPU>;
#iommu-cells = <0>;
};
@@ -951,14 +1096,14 @@
#address-cells = <1>;
#size-cells = <0>;
dsi_in_vopl: endpoint@0 {
dsi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopl_out_dsi>;
remote-endpoint = <&vopb_out_dsi>;
};
dsi_in_vopb: endpoint@1 {
dsi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopb_out_dsi>;
remote-endpoint = <&vopl_out_dsi>;
};
};
};
@@ -972,6 +1117,7 @@
clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
<&cru HCLK_VOPB>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power PX30_PD_VO>;
iommus = <&vopb_mmu>;
status = "disabled";
@@ -998,6 +1144,7 @@
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
clock-names = "aclk", "hclk";
power-domains = <&power PX30_PD_VO>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -1010,6 +1157,7 @@
clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
<&cru HCLK_VOPL>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power PX30_PD_VO>;
iommus = <&vopl_mmu>;
status = "disabled";
@@ -1036,6 +1184,7 @@
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
clock-names = "aclk", "hclk";
power-domains = <&power PX30_PD_VO>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -1045,8 +1194,9 @@
//dev_mode = <1>;
reg = <0x0 0xff480000 0x0 0x1000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>;
clock-names = "aclk_rga", "hclk_rga";
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
power-domains = <&power PX30_PD_VO>;
dma-coherent;
status = "disabled";
};
@@ -1059,8 +1209,10 @@
clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out";
resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>;
reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin";
power-domains = <&power PX30_PD_VI>;
pinctrl-names = "cif_pin_all";
pinctrl-0 = <&dvp_d2d9_m0>;
iommus = <&vip_mmu>;
status = "disabled";
};
@@ -1071,6 +1223,7 @@
interrupt-names = "vip_mmu";
clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>;
clock-names = "aclk", "hclk";
power-domains = <&power PX30_PD_VI>;
rk_iommu,disable_reset_quirk;
#iommu-cells = <0>;
status = "disabled";
@@ -1078,7 +1231,7 @@
rk_isp: rk_isp@ff4a0000 {
compatible = "rockchip,px30-isp", "rockchip,isp";
reg = <0x0 0xff4a0000 0x0 0x4000>;
reg = <0x0 0xff4a0000 0x0 0x8000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>,
<&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>;
@@ -1086,9 +1239,10 @@
"pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx";
resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>;
reset-names = "rst_isp", "rst_mipicsiphy";
power-domains = <&power PX30_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clkout_m0>;
rockchip,isp,mipiphy = <0>;
rockchip,isp,mipiphy = <1>;
rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>;
rockchip,grf = <&grf>;
rockchip,cru = <&cru>;
@@ -1104,6 +1258,7 @@
interrupt-names = "isp_mmu";
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
clock-names = "aclk", "hclk";
power-domains = <&power PX30_PD_VI>;
rk_iommu,disable_reset_quirk;
#iommu-cells = <0>;
status = "disabled";
@@ -1209,6 +1364,74 @@
reg = <0x0 0xff558080 0x0 0x20>;
};
dfi: dfi@ff610000 {
reg = <0x00 0xff610000 0x00 0x400>;
compatible = "rockchip,px30-dfi";
rockchip,pmugrf = <&pmugrf>;
status = "disabled";
};
dmc: dmc {
compatible = "rockchip,px30-dmc";
devfreq-events = <&dfi>;
clocks = <&cru SCLK_DDRCLK>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
ddr_timing = <&ddr_timing>;
upthreshold = <40>;
downdifferential = <20>;
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 786000
SYS_STATUS_REBOOT 786000
SYS_STATUS_SUSPEND 786000
SYS_STATUS_VIDEO_1080P 786000
SYS_STATUS_PERFORMANCE 786000
SYS_STATUS_BOOST 786000
>;
auto-min-freq = <400000>;
auto-freq-en = <0>;
#cooling-cells = <2>;
status = "disabled";
ddr_power_model: ddr_power_model {
compatible = "ddr_power_model";
dynamic-power-coefficient = <120>;
static-power-coefficient = <200>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "soc-thermal";
};
};
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <925000>;
opp-microvolt-L0 = <925000>;
opp-microvolt-L1 = <900000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1025000>;
opp-microvolt-L0 = <1025000>;
opp-microvolt-L1 = <1000000>;
};
opp-786000000 {
opp-hz = /bits/ 64 <786000000>;
opp-microvolt = <1075000>;
opp-microvolt-L0 = <1075000>;
opp-microvolt-L1 = <1050000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1075000>;
opp-microvolt-L0 = <1075000>;
opp-microvolt-L1 = <1050000>;
};
};
pinctrl: pinctrl {
compatible = "rockchip,px30-pinctrl";
rockchip,grf = <&grf>;
@@ -1221,7 +1444,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff040000 0x0 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0_PMU>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
gpio-controller;
#gpio-cells = <2>;
@@ -1564,11 +1787,16 @@
<3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>;
};
spi1_csn: spi1-csn {
spi1_csn0: spi1-csn0 {
rockchip,pins =
<3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>;
};
spi1_csn1: spi1-csn1 {
rockchip,pins =
<3 RK_PB2 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_miso: spi1-miso {
rockchip,pins =
<3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>;
@@ -1598,7 +1826,7 @@
pdm_sdi0m0: pdm-sdi0m0 {
rockchip,pins =
<3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>;
<3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>;
};
pdm_sdi0m1: pdm-sdi0m1 {
@@ -1618,7 +1846,7 @@
pdm_sdi3: pdm-sdi3 {
rockchip,pins =
<3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>;
<3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
};
pdm_clk0m0_sleep: pdm-clk0m0-sleep {
@@ -1688,11 +1916,6 @@
<3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
};
i2s0_8ch_sdo: i2s0-8ch-sdo {
rockchip,pins =
<3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>;
};
i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
rockchip,pins =
<3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
@@ -1713,11 +1936,6 @@
<3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>;
};
i2s0_8ch_sdi: i2s0-8ch-sdi {
rockchip,pins =
<3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>;
};
i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
rockchip,pins =
<3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>;
@@ -1793,23 +2011,28 @@
};
};
sdmmc0 {
sdmmc0_clk: sdmmc0-clk {
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins =
<1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_4ma>;
};
sdmmc0_cmd: sdmmc0-cmd {
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
<1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_4ma>;
};
sdmmc0_bus1: sdmmc0-bus1 {
sdmmc_det: sdmmc-det {
rockchip,pins =
<0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_4ma>;
};
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins =
<1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_4ma>;
};
sdmmc0_bus4: sdmmc0-bus4 {
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
<1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_4ma>,
<1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_4ma>,
@@ -1817,7 +2040,7 @@
<1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_4ma>;
};
sdmmc0_gpio: sdmmc0-gpio {
sdmmc_gpio: sdmmc-gpio {
rockchip,pins =
<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
<1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
@@ -1828,38 +2051,33 @@
};
};
sdmmc1 {
sdmmc1_clk: sdmmc1-clk {
sdio {
sdio_clk: sdio-clk {
rockchip,pins =
<1 RK_PC5 RK_FUNC_1 &pcfg_pull_none_8ma>;
<1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
};
sdmmc1_cmd: sdmmc1-cmd {
sdio_cmd: sdio-cmd {
rockchip,pins =
<1 RK_PC4 RK_FUNC_1 &pcfg_pull_up_8ma>;
<1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc1_bus1: sdmmc1-bus1 {
sdio_bus4: sdio-bus4 {
rockchip,pins =
<1 RK_PC6 RK_FUNC_1 &pcfg_pull_up_8ma>;
<1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
<1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>,
<1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>,
<1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc1_bus4: sdmmc1-bus4 {
sdio_gpio: sdio-gpio {
rockchip,pins =
<1 RK_PC6 RK_FUNC_1 &pcfg_pull_up_8ma>,
<1 RK_PC7 RK_FUNC_1 &pcfg_pull_up_8ma>,
<1 RK_PD0 RK_FUNC_1 &pcfg_pull_up_8ma>,
<1 RK_PD1 RK_FUNC_1 &pcfg_pull_up_8ma>;
};
sdmmc1_gpio: sdmmc1-gpio {
rockchip,pins =
<1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
<1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
<1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
<1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3326-863-cif-sensor.dtsi
View File

@@ -12,7 +12,7 @@
gc2145_b {
is_front = <0>;
powerdown-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
pwdn_active = <gc2145_PWRDN_ACTIVE>;
pwr_active = <PWR_ACTIVE_HIGH>;
mir = <0>;
@@ -28,7 +28,7 @@
gc0312_f {
is_front = <1>;
powerdown-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
pwdn_active = <gc0312_PWRDN_ACTIVE>;
pwr_active = <PWR_ACTIVE_HIGH>;
mir = <0>;

406
arch/arm64/boot/dts/rockchip/rk3326-863-lp3-v10.dts
View File

@@ -22,18 +22,19 @@
compatible = "adc-keys";
io-channels = <&saradc 2>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <10000>;
};
vol-down-key {
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <170000>;
press-threshold-microvolt = <300000>;
};
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <17000>;
};
};
@@ -76,6 +77,34 @@
default-brightness-level = <200>;
};
rk817-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rk817-codec";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Mic Jack", "MICBIAS1",
"IN1P", "Mic Jack",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
simple-audio-card,cpu {
sound-dai = <&i2s1_2ch>;
};
simple-audio-card,codec {
sound-dai = <&rk817_codec>;
};
};
rk_headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&cru SCLK_WIFI_PMU>;
@@ -92,10 +121,20 @@
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
};
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc3v8_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
};
wireless-wlan {
compatible = "wlan-platdata";
wifi_chip_type = "rtl8723cs";
WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
WIFI,vbat_gpio = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -131,7 +170,7 @@
compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi";
reg = <0>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
prepare-delay-ms = <20>;
reset-delay-ms = <20>;
@@ -162,7 +201,7 @@
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <65000000>;
clock-frequency = <66000000>;
hactive = <800>;
vactive = <1280>;
hfront-porch = <2>;
@@ -180,6 +219,10 @@
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&dsi_in_vopl {
status = "disabled";
};
@@ -192,15 +235,274 @@
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_logic>;
status = "okay";
};
&i2c0 {
status = "okay";
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
vcc3-supply = <&vccsys>;
vcc4-supply = <&vccsys>;
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vcc_3v0>;
vcc8-supply = <&vccsys>;
vcc9-supply = <&dcdc_boost>;
pwrkey {
status = "okay";
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc2v5_ddr: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5_ddr";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v0_soc: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc1v0_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_dvp: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v5_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd1v5_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
dcdc_boost: BOOST {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <4700000>;
regulator-max-microvolt = <5400000>;
regulator-name = "boost";
};
otg_switch: OTG_SWITCH {
regulator-boot-on;
regulator-name = "otg_switch";
};
};
battery {
compatible = "rk817,battery";
ocv_table = <3500 3625 3685 3697 3718 3735 3748
3760 3774 3788 3802 3816 3834 3853
3877 3908 3946 3975 4018 4071 4106>;
design_capacity = <2500>;
design_qmax = <2750>;
bat_res = <100>;
sleep_enter_current = <300>;
sleep_exit_current = <300>;
sleep_filter_current = <100>;
power_off_thresd = <3500>;
zero_algorithm_vol = <3850>;
max_soc_offset = <60>;
monitor_sec = <5>;
sample_res = <10>;
virtual_power = <1>;
};
charger {
compatible = "rk817,charger";
min_input_voltage = <4500>;
max_input_current = <1500>;
max_chrg_current = <1300>;
max_chrg_voltage = <4200>;
chrg_term_mode = <1>;
chrg_finish_cur = <300>;
virtual_power = <0>;
dc_det_adc = <0>;
extcon = <&u2phy>;
};
rk817_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk817-codec";
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
hp-volume = <20>;
spk-volume = <3>;
mic-in-differential;
status = "okay";
};
};
};
&i2c1 {
status = "okay";
@@ -220,20 +522,52 @@
irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
irq_enable = <0>;
poll_delay_ms = <30>;
layout = <6>;
layout = <7>;
reprobe_en = <1>;
};
};
&i2c2 {
status = "okay";
};
&i2s1_2ch {
status = "okay";
#sound-dai-cells = <0>;
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_3v0>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc2v8_dvp>;
vccio4-supply = <&vcc_3v0>;
vccio5-supply = <&vcc_3v0>;
};
&mipi_dphy {
status = "okay";
};
&pwm1 {
&nandc0 {
status = "okay";
};
&pinctrl {
headphone {
hp_det: hp-det {
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -241,12 +575,28 @@
};
};
&route_dsi {
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v0_pmu>;
pmuio2-supply = <&vcc3v0_pmu>;
};
&pwm1 {
status = "okay";
};
&rk_rga {
status = "okay";
};
&route_dsi {
status = "disabled";
};
&saradc {
status = "okay";
vref-supply = <&vcc1v8_soc>;
};
&sdmmc {
@@ -271,12 +621,36 @@
status = "okay";
};
&tsadc {
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "okay";
};
};
&usb20_otg {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
&vip_mmu {
status = "okay";
};
&vopb {
status = "okay";
};
@@ -292,3 +666,7 @@
&vopl_mmu {
status = "okay";
};
&vpu_combo {
status = "okay";
};

485
arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10.dts
View File

@@ -22,36 +22,37 @@
compatible = "adc-keys";
io-channels = <&saradc 2>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <10000>;
};
vol-down-key {
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <170000>;
esc-key {
linux,code = <KEY_ESC>;
label = "esc";
press-threshold-microvolt = <1310000>;
};
home-key {
linux,code = <KEY_HOME>;
label = "home";
press-threshold-microvolt = <254000>;
press-threshold-microvolt = <624000>;
};
menu-key {
linux,code = <KEY_MENU>;
label = "menu";
press-threshold-microvolt = <414000>;
press-threshold-microvolt = <987000>;
};
esc-key {
linux,code = <KEY_ESC>;
label = "esc";
press-threshold-microvolt = <614000>;
vol-down-key {
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <300000>;
};
vol-up-key {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <17000>;
};
};
@@ -95,14 +96,16 @@
};
panel {
compatible = "auo,b101ew05", "simple-panel";
compatible = "samsung,lsl070nl01", "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
disable-delay-ms = <10>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
width-mm = <217>;
height-mm = <136>;
rockchip,data-mapping = "jeida";
rockchip,data-mapping = "vesa";
rockchip,data-width = <24>;
rockchip,output = "lvds";
status = "disabled";
@@ -111,15 +114,15 @@
native-mode = <&b101ew05_timing>;
b101ew05_timing: timing0 {
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <220>;
hfront-porch = <110>;
vback-porch = <20>;
vfront-porch = <5>;
hsync-len = <40>;
vsync-len = <5>;
clock-frequency = <49500000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <90>;
hfront-porch = <90>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <90>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
@@ -134,6 +137,35 @@
};
};
rk817-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rk817-codec";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Mic Jack", "MICBIAS1",
"IN1P", "Mic Jack",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
simple-audio-card,cpu {
sound-dai = <&i2s1_2ch>;
};
simple-audio-card,codec {
sound-dai = <&rk817_codec>;
};
};
rk_headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
io-channels = <&saradc 1>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
/*clocks = <&rk817 1>;*/
@@ -150,6 +182,15 @@
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
};
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc3v8_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
};
wireless-wlan {
compatible = "wlan-platdata";
wifi_chip_type = "AP6210";
@@ -159,8 +200,8 @@
wireless-bluetooth {
compatible = "bluetooth-platdata";
/*clocks = <&rk817 1>;*/
/*clock-names = "ext_clock";*/
clocks = <&rk817 1>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default","rts_gpio";
pinctrl-0 = <&uart1_rts>;
@@ -172,12 +213,8 @@
};
};
&cif {
status = "okay";
};
&cif_sensor {
status = "okay";
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&display_subsystem {
@@ -191,7 +228,7 @@
compatible = "sitronix,st7703", "simple-panel-dsi";
reg = <0>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <2>;
reset-delay-ms = <1>;
init-delay-ms = <20>;
@@ -259,7 +296,7 @@
native-mode = <&st7703_timing>;
st7703_timing: timing0 {
clock-frequency = <64000000>;
clock-frequency = <66000000>;
hactive = <720>;
vactive = <1280>;
hfront-porch = <40>;
@@ -289,17 +326,281 @@
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_logic>;
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <280>;
i2c-scl-falling-time-ns = <16>;
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
vcc3-supply = <&vccsys>;
vcc4-supply = <&vccsys>;
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vcc_3v0>;
vcc8-supply = <&vccsys>;
vcc9-supply = <&dcdc_boost>;
pwrkey {
status = "okay";
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc2v5_ddr: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5_ddr";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v0_soc: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc1v0_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_dvp: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v5_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd1v5_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
dcdc_boost: BOOST {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <4700000>;
regulator-max-microvolt = <5400000>;
regulator-name = "boost";
};
otg_switch: OTG_SWITCH {
regulator-boot-on;
regulator-name = "otg_switch";
};
};
battery {
compatible = "rk817,battery";
ocv_table = <3500 3625 3685 3697 3718 3735 3748
3760 3774 3788 3802 3816 3834 3853
3877 3908 3946 3975 4018 4071 4106>;
design_capacity = <2500>;
design_qmax = <2750>;
bat_res = <100>;
sleep_enter_current = <300>;
sleep_exit_current = <300>;
sleep_filter_current = <100>;
power_off_thresd = <3500>;
zero_algorithm_vol = <3850>;
max_soc_offset = <60>;
monitor_sec = <5>;
sample_res = <10>;
virtual_power = <1>;
};
charger {
compatible = "rk817,charger";
min_input_voltage = <4500>;
max_input_current = <1500>;
max_chrg_current = <1300>;
max_chrg_voltage = <4200>;
chrg_term_mode = <1>;
chrg_finish_cur = <300>;
virtual_power = <0>;
dc_det_adc = <0>;
extcon = <&u2phy>;
};
rk817_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk817-codec";
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
hp-volume = <20>;
spk-volume = <3>;
status = "okay";
};
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <275>;
i2c-scl-falling-time-ns = <16>;
sensor@0f {
status = "okay";
@@ -312,12 +613,11 @@
reprobe_en = <1>;
};
ts@40 {
status = "okay";
compatible = "GT1X";
reg = <0x14>;
irq_gpio_number = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
rst_gpio_number = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
gt1x: gt1x@14 {
compatible = "goodix,gt1x";
reg = <0x14>;
goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
};
sensor@4c {
@@ -328,15 +628,35 @@
irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
irq_enable = <0>;
poll_delay_ms = <30>;
layout = <6>;
layout = <1>;
reprobe_en = <1>;
};
};
&i2c2 {
status = "okay";
};
&i2s1_2ch {
status = "okay";
#sound-dai-cells = <0>;
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc1v8_soc>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc1v8_dvp>;
vccio4-supply = <&vcc_3v0>;
vccio5-supply = <&vcc_3v0>;
};
&isp_mmu {
status = "okay";
};
&lvds {
//pinctrl-names = "lcdc";
//pinctrl-0 = <&lcdc_rgb_dclk_pin &lcdc_rgb_m0_den_pin &lcdc_rgb_m0_hsync_pin &lcdc_rgb_m0_vsync_pin &lcdc_rgb666_m0_data_pins>;
//pinctrl-0 = <&lcdc_rgb_dclk_pin &lcdc_rgb666_m1_data_pins>;
status = "disabled";
ports {
@@ -358,11 +678,24 @@
status = "okay";
};
&pwm1 {
&nandc0 {
status = "okay";
};
&pinctrl {
headphone {
hp_det: hp-det {
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -370,8 +703,36 @@
};
};
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v0_pmu>;
pmuio2-supply = <&vcc3v0_pmu>;
};
&pwm1 {
status = "okay";
};
&rk_isp {
status = "okay";
};
&rk_rga {
status = "okay";
};
&route_dsi {
status = "disabled";
};
&route_lvds {
status = "disabled";
};
&saradc {
status = "okay";
vref-supply = <&vcc1v8_soc>;
};
&sdmmc {
@@ -396,14 +757,10 @@
status = "okay";
};
&route_dsi {
&tsadc {
status = "okay";
};
&route_lvds {
status = "disabled";
};
&u2phy {
status = "okay";
@@ -420,14 +777,6 @@
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts>;
@@ -449,3 +798,7 @@
&vopl_mmu {
status = "okay";
};
&vpu_combo {
status = "okay";
};

8
arch/arm64/boot/dts/rockchip/rk3328-android.dtsi
View File

@@ -82,6 +82,14 @@
charge_logo,mode = "fullscreen";
connect = <&vop_out_hdmi>;
};
route_tve: route-tve {
status = "okay";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "fullscreen";
charge_logo,mode = "fullscreen";
connect = <&vop_out_tve>;
};
};
};

2
arch/arm64/boot/dts/rockchip/rk3328-evb-android.dts
View File

@@ -541,7 +541,7 @@
&spdif {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spdifm0_tx>;
pinctrl-0 = <&spdifm2_tx>;
status = "okay";
};

585
arch/arm64/boot/dts/rockchip/rk3328-rock64-android.dts Normal file
View File

@@ -0,0 +1,585 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "rk3328.dtsi"
#include "rk3328-android.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Pine64 Rock64";
compatible = "pine64,rock64-android", "rockchip,rk3328";
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_gpio>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc_host_5v: vcc-host-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb30_host_drv>;
regulator-name = "vcc_host_5v";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,rk3328";
simple-audio-card,cpu {
sound-dai = <&i2s1>;
};
simple-audio-card,codec {
sound-dai = <&codec>;
};
};
hdmi-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <128>;
simple-audio-card,name = "rockchip,hdmi";
simple-audio-card,cpu {
sound-dai = <&i2s0>;
};
simple-audio-card,codec {
sound-dai = <&hdmi>;
};
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
};
&codec {
#sound-dai-cells = <0>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&dfi {
status = "okay";
};
&dmc {
center-supply = <&vdd_logic>;
status = "okay";
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
supports-emmc;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gmac2io {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
};
&gmac2phy {
phy-supply = <&vcc_phy>;
clock_in_out = "output";
assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
assigned-clock-rate = <50000000>;
assigned-clocks = <&cru SCLK_MAC2PHY>;
assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
status = "disabled";
};
&gpu {
status = "okay";
mali-supply = <&vdd_logic>;
};
&hdmi {
#sound-dai-cells = <0>;
status = "okay";
};
&hdmiphy {
status = "okay";
};
&i2c1 {
status = "okay";
rk805: rk805@18 {
compatible = "rockchip,rk805";
status = "okay";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
wakeup-source;
gpio-controller;
#gpio-cells = <2>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
rtc {
status = "okay";
};
pwrkey {
status = "disabled";
};
gpio {
status = "okay";
};
regulators {
compatible = "rk805-regulator";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
vdd_logic: RK805_DCDC1@0 {
regulator-compatible = "RK805_DCDC1";
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <0x1>;
regulator-ramp-delay = <12500>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: RK805_DCDC2@1 {
regulator-compatible = "RK805_DCDC2";
regulator-name = "vdd_arm";
regulator-init-microvolt = <1225000>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <0x1>;
regulator-ramp-delay = <12500>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: RK805_DCDC3@2 {
regulator-compatible = "RK805_DCDC3";
regulator-name = "vcc_ddr";
regulator-initial-mode = <0x1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
};
};
vcc_io: RK805_DCDC4@3 {
regulator-compatible = "RK805_DCDC4";
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd_18: RK805_LDO1@4 {
regulator-compatible = "RK805_LDO1";
regulator-name = "vdd_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_18emmc: RK805_LDO2@5 {
regulator-compatible = "RK805_LDO2";
regulator-name = "vcc_18emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_11: RK805_LDO3@6 {
regulator-compatible = "RK805_LDO3";
regulator-name = "vdd_11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1100000>;
};
};
};
};
};
&h265e {
status = "okay";
};
&i2s0 {
#sound-dai-cells = <0>;
rockchip,bclk-fs = <128>;
status = "okay";
};
&i2s1 {
#sound-dai-cells = <0>;
status = "okay";
};
&iep {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc_18emmc>;
vccio3-supply = <&vcc_io>;
vccio4-supply = <&vdd_18>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
pmuio-supply = <&vcc_io>;
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
usb20_host_drv: usb20-host-drv {
rockchip,pins = <0 27 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb3 {
usb30_host_drv: usb30-host-drv {
rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm3 {
status = "okay";
compatible = "rockchip,remotectl-pwm";
remote_pwm_id = <3>;
handle_cpu_id = <1>;
remote_support_psci = <1>;
ir_key1 {
rockchip,usercode = <0x4040>;
rockchip,key_table =
<0xf2 KEY_REPLY>,
<0xba KEY_BACK>,
<0xf4 KEY_UP>,
<0xf1 KEY_DOWN>,
<0xef KEY_LEFT>,
<0xee KEY_RIGHT>,
<0xbd KEY_HOME>,
<0xea KEY_VOLUMEUP>,
<0xe3 KEY_VOLUMEDOWN>,
<0xe2 KEY_SEARCH>,
<0xb2 KEY_POWER>,
<0xbc KEY_MUTE>,
<0xec KEY_MENU>,
<0xbf 0x190>,
<0xe0 0x191>,
<0xe1 0x192>,
<0xe9 183>,
<0xe6 248>,
<0xe8 185>,
<0xe7 186>,
<0xf0 388>,
<0xbe 0x175>;
};
ir_key2 {
rockchip,usercode = <0xff00>;
rockchip,key_table =
<0xf9 KEY_HOME>,
<0xbf KEY_BACK>,
<0xfb KEY_MENU>,
<0xaa KEY_REPLY>,
<0xb9 KEY_UP>,
<0xe9 KEY_DOWN>,
<0xb8 KEY_LEFT>,
<0xea KEY_RIGHT>,
<0xeb KEY_VOLUMEDOWN>,
<0xef KEY_VOLUMEUP>,
<0xf7 KEY_MUTE>,
<0xe7 KEY_POWER>,
<0xfc KEY_POWER>,
<0xa9 KEY_VOLUMEDOWN>,
<0xa8 KEY_PLAYPAUSE>,
<0xe0 KEY_VOLUMEDOWN>,
<0xa5 KEY_VOLUMEDOWN>,
<0xab 183>,
<0xb7 388>,
<0xe8 388>,
<0xf8 184>,
<0xaf 185>,
<0xed KEY_VOLUMEDOWN>,
<0xee 186>,
<0xb3 KEY_VOLUMEDOWN>,
<0xf1 KEY_VOLUMEDOWN>,
<0xf2 KEY_VOLUMEDOWN>,
<0xf3 KEY_SEARCH>,
<0xb4 KEY_VOLUMEDOWN>,
<0xa4 KEY_SETUP>,
<0xbe KEY_SEARCH>;
};
ir_key3 {
rockchip,usercode = <0x1dcc>;
rockchip,key_table =
<0xee KEY_REPLY>,
<0xf0 KEY_BACK>,
<0xf8 KEY_UP>,
<0xbb KEY_DOWN>,
<0xef KEY_LEFT>,
<0xed KEY_RIGHT>,
<0xfc KEY_HOME>,
<0xf1 KEY_VOLUMEUP>,
<0xfd KEY_VOLUMEDOWN>,
<0xb7 KEY_SEARCH>,
<0xff KEY_POWER>,
<0xf3 KEY_MUTE>,
<0xbf KEY_MENU>,
<0xf9 0x191>,
<0xf5 0x192>,
<0xb3 388>,
<0xbe KEY_1>,
<0xba KEY_2>,
<0xb2 KEY_3>,
<0xbd KEY_4>,
<0xf9 KEY_5>,
<0xb1 KEY_6>,
<0xfc KEY_7>,
<0xf8 KEY_8>,
<0xb0 KEY_9>,
<0xb6 KEY_0>,
<0xb5 KEY_BACKSPACE>;
};
};
&rga {
status = "okay";
};
&rkvdec {
status = "okay";
vcodec-supply = <&vdd_logic>;
};
&rockchip_suspend {
status = "okay";
rockchip,virtual-poweroff = <1>;
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
supports-sd;
status = "okay";
vmmc-supply = <&vcc_sd>;
};
&spi0 {
status = "okay";
flash@0 {
compatible = "gigadevice,gd25q128", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
m25p,fast-read;
/* The max SCLK of the flash 104/80 MHZ */
spi-max-frequency = <50000000>;
};
};
&threshold {
temperature = <90000>; /* millicelsius */
};
&target {
temperature = <105000>; /* millicelsius */
};
&soc_crit {
temperature = <110000>; /* millicelsius */
};
&tsadc {
rockchip,hw-tshut-temp = <120000>;
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
phy-supply = <&vcc_host1_5v>;
status = "okay";
};
&u2phy_otg {
phy-supply = <&vcc_otg_5v>;
status = "okay";
};
&u3phy {
phy-supply = <&vcc_host_5v>;
status = "okay";
};
&u3phy_utmi {
status = "okay";
};
&u3phy_pipe {
status = "okay";
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usbdrd3 {
status = "okay";
};
&usbdrd_dwc3 {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vpu_service {
status = "okay";
};
&vepu {
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@@ -1075,8 +1075,7 @@
<&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
<&cru SCLK_UART1>, <&cru SCLK_UART2>,
<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
<&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
<&cru ACLK_RGA_PRE>, <&cru ACLK_RKVDEC_PRE>,
<&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
@@ -1105,7 +1104,6 @@
<24000000>, <24000000>,
<15000000>, <15000000>,
<100000000>, <100000000>,
<100000000>, <100000000>,
<50000000>, <100000000>,
<100000000>, <100000000>,
<50000000>, <50000000>,

3
arch/arm64/boot/dts/rockchip/rk3366.dtsi
View File

@@ -1078,9 +1078,6 @@
clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";
power-domains = <&power RK3366_PD_VIO>;
pinctrl-names = "lcdc", "gpio";
pinctrl-0 = <&lcdc_lcdc>;
pinctrl-1 = <&lcdc_gpio>;
rockchip,grf = <&grf>;
status = "disabled";

1
arch/arm64/boot/dts/rockchip/rk3368-cif-sensor.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "../../../../../drivers/soc/rockchip/rk_camera_sensor_info.h"
/{

22
arch/arm64/boot/dts/rockchip/rk3368-px5-evb-android.dts
View File

@@ -250,6 +250,28 @@
status = "okay";
};
gpio_det: gpio-det {
compatible = "gpio-detection";
status = "okay";
pinctrl-0 = <&gpio3_b1 &gpio3_b2>;
pinctrl-names = "default";
car-reverse {
car-reverse-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
linux,debounce-ms = <5>;
label = "car-reverse";
gpio,wakeup;
};
car-acc {
car-acc-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
linux,debounce-ms = <5>;
label = "car-acc";
gpio,wakeup;
};
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";

50
arch/arm64/boot/dts/rockchip/rk3368-r88.dts
View File

@@ -173,6 +173,35 @@
};
};
&dfi {
status = "okay";
};
&dmc {
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 528000
SYS_STATUS_REBOOT 600000
SYS_STATUS_SUSPEND 192000
SYS_STATUS_VIDEO_1080P 400000
SYS_STATUS_VIDEO_4K 800000
SYS_STATUS_PERFORMANCE 800000
SYS_STATUS_BOOST 400000
SYS_STATUS_DUALVIEW 400000
SYS_STATUS_ISP 400000
>;
center-supply = <&vdd_gpu>;
auto-freq-en = <0>;
status = "okay";
};
&dmc_opp_table {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1175000>;
};
};
&i2s_8ch {
status = "okay";
rockchip,i2s-broken-burst-len;
@@ -445,14 +474,12 @@
rockchip,data-width = <24>;
rockchip,output = "rgb";
rockchip,ctl = <&rk1000_ctl>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tve_in: port@0 {
reg = <0>;
tve_in_lvds: endpoint {
remote-endpoint = <&lvds_out_tve>;
};
#address-cells = <1>;
#size-cells = <0>;
tve_in: port@0 {
reg = <0>;
tve_in_lvds: endpoint {
remote-endpoint = <&lvds_out_tve>;
};
};
};
@@ -469,6 +496,9 @@
};
&lvds {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcdc_lcdc>;
pinctrl-1 = <&lcdc_gpio>;
status = "okay";
ports {
@@ -642,6 +672,10 @@
status = "okay";
};
&route_lvds {
status = "okay";
};
&hdmi {
status = "okay";
#sound-dai-cells = <0>;

3
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@@ -1540,9 +1540,6 @@
clock-names = "pclk_lvds", "pclk_lvds_ctl";
power-domains = <&power RK3368_PD_VIO>;
rockchip,grf = <&grf>;
pinctrl-names = "lcdc", "gpio";
pinctrl-0 = <&lcdc_lcdc>;
pinctrl-1 = <&lcdc_gpio>;
status = "disabled";
ports {

2
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-linux.dts
View File

@@ -218,6 +218,8 @@
};
&hdmi {
/* remove the hdmi_cec, reused by edp_hpd */
pinctrl-0 = <&hdmi_i2c_xfer>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <0>;

8
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
View File

@@ -192,6 +192,12 @@
};
};
&cdn_dp {
status = "okay";
extcon = <&fusb0>;
phys = <&tcphy0_dp>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
@@ -516,7 +522,7 @@
};
&pcie0 {
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;

27
arch/arm64/configs/rockchip_defconfig
View File

@@ -7,13 +7,16 @@ CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_SCHEDTUNE=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_NAMESPACES=y
@@ -30,7 +33,6 @@ CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_LZ4 is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
@@ -73,7 +75,6 @@ CONFIG_ARM64_SW_TTBR0_PAN=y
# CONFIG_EFI is not set
# CONFIG_COREDUMP is not set
CONFIG_COMPAT=y
CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -164,7 +165,6 @@ CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
@@ -240,6 +240,7 @@ CONFIG_BLK_DEV_NVME=y
CONFIG_ROCKCHIP_SCR=y
CONFIG_SRAM=y
CONFIG_UID_SYS_STATS=y
CONFIG_MEMORY_STATE_TIME=y
CONFIG_USB_CAM_GPIO=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
@@ -364,6 +365,7 @@ CONFIG_RTL8822BE=m
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_KEYRESET=y
CONFIG_KEYBOARD_ADC=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_ROCKCHIP=y
# CONFIG_INPUT_MOUSE is not set
@@ -397,6 +399,7 @@ CONFIG_HALL_DEVICE=y
CONFIG_HS_MH248=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_KEYCHORD=y
CONFIG_INPUT_RK8XX_PWRKEY=y
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_GPIO=y
# CONFIG_SERIO is not set
@@ -425,6 +428,8 @@ CONFIG_TEST_POWER=y
CONFIG_CHARGER_BQ25700=y
CONFIG_BATTERY_EC=y
CONFIG_BATTERY_CW2015=y
CONFIG_BATTERY_RK817=y
CONFIG_CHARGER_RK817=y
CONFIG_BATTERY_RK818=y
CONFIG_CHARGER_RK818=y
CONFIG_POWER_RESET_GPIO=y
@@ -493,11 +498,17 @@ CONFIG_MALI450=y
CONFIG_MALI_SHARED_INTERRUPTS=y
CONFIG_MALI_DT=y
CONFIG_MALI_DEVFREQ=y
CONFIG_MALI_MIDGARD=y
CONFIG_MALI_MIDGARD=m
CONFIG_MALI_EXPERT=y
CONFIG_MALI_PLATFORM_THIRDPARTY=y
CONFIG_MALI_PLATFORM_THIRDPARTY_NAME="rk"
CONFIG_MALI_DEBUG=y
CONFIG_MALI_BIFROST=m
CONFIG_MALI_BIFROST_DEVFREQ=y
CONFIG_MALI_PLATFORM_NAME="rk"
CONFIG_MALI_BIFROST_EXPERT=y
CONFIG_MALI_BIFROST_DEBUG=y
CONFIG_MALI_PWRSOFT_765=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
@@ -534,6 +545,7 @@ CONFIG_SND_VERBOSE_PRINTK=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_PDM=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
CONFIG_SND_SOC_ROCKCHIP_HDMI_ANALOG=y
CONFIG_SND_SOC_ROCKCHIP_HDMI_DP=y
@@ -547,6 +559,7 @@ CONFIG_SND_SOC_ES8396=y
CONFIG_SND_SOC_FM1288=y
CONFIG_SND_SOC_RK1000=y
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SIMPLE_CARD=y
@@ -648,7 +661,6 @@ CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_OPTION=y
CONFIG_USB_TRANCEVIBRATOR=y
CONFIG_USB_OTG_WAKELOCK=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_GADGET_VBUS_DRAW=500
@@ -686,7 +698,6 @@ CONFIG_STAGING=y
CONFIG_INV_MPU_IIO=y
CONFIG_ASHMEM=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
CONFIG_SYNC=y
CONFIG_SW_SYNC=y
CONFIG_SW_SYNC_USER=y
@@ -708,6 +719,7 @@ CONFIG_RK3368_SCPI_PROTOCOL=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_RK_IOMMU=y
CONFIG_RK_IOVMM=y
CONFIG_ANDROID_VERSION=0x08000000
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_PVTM=y
CONFIG_ROCKCHIP_SUSPEND_MODE=y
@@ -803,3 +815,4 @@ CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_CRC32_ARM64=y

1
arch/arm64/configs/rockchip_linux_defconfig
View File

@@ -301,6 +301,7 @@ CONFIG_DRM=y
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DMA_SYNC=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y

1
arch/arm64/include/asm/system_info.h
View File

@@ -1,3 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_ARM_SYSTEM_INFO_H
#define __ASM_ARM_SYSTEM_INFO_H

4
arch/arm64/kvm/handle_exit.c
View File

@@ -43,7 +43,7 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
ret = kvm_psci_call(vcpu);
if (ret < 0) {
kvm_inject_undefined(vcpu);
vcpu_set_reg(vcpu, 0, ~0UL);
return 1;
}
@@ -52,7 +52,7 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
kvm_inject_undefined(vcpu);
vcpu_set_reg(vcpu, 0, ~0UL);
return 1;
}

2
arch/mips/ar7/platform.c
View File

@@ -576,7 +576,7 @@ static int __init ar7_register_uarts(void)
uart_port.type = PORT_AR7;
uart_port.uartclk = clk_get_rate(bus_clk) / 2;
uart_port.iotype = UPIO_MEM32;
uart_port.flags = UPF_FIXED_TYPE;
uart_port.flags = UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF;
uart_port.regshift = 2;
uart_port.line = 0;

2
arch/um/Makefile
View File

@@ -117,7 +117,7 @@ archheaders:
archprepare: include/generated/user_constants.h
LINK-$(CONFIG_LD_SCRIPT_STATIC) += -static
LINK-$(CONFIG_LD_SCRIPT_DYN) += -Wl,-rpath,/lib
LINK-$(CONFIG_LD_SCRIPT_DYN) += -Wl,-rpath,/lib $(call cc-option, -no-pie)
CFLAGS_NO_HARDENING := $(call cc-option, -fno-PIC,) $(call cc-option, -fno-pic,) \
$(call cc-option, -fno-stack-protector,) \

Some files were not shown because too many files have changed in this diff Show More