shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-05 10:31:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

regulator: rk806: Resolving rk806m abnormal power-off during DVS Mode

Browse Source 
If the RK806M DVS mode does not follow the configured timing sequence,
it may cause abnormal power-off.

The settings must be configured in the following order:
entering voltage adjustment:
	first configure SLPn_FUN, then configure XXX_SLP_CTR_SEL at addresses 0x64~0x6e.
exiting voltage adjustment:
	first clear XXX_SLP_CTR_SEL at addresses 0x64~0x6e to 0, then modify SLPn_FUN.

Change-Id: I265d916b99160fddf467f7c12149490a95f75ca8
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
This commit is contained in:
Shengfei Xu
2025-09-24 10:37:00 +08:00
committed by Tao Huang
parent 02aea86b57
commit f97148ab59
1 changed files with 14 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/regulator/rk806-regulator.c
View File

@@ -1195,6 +1195,20 @@ static int __maybe_unused rk806_suspend(struct device *dev)
for (i = RK806_ID_DCDC1; i < RK806_ID_END; i++)
rk806_field_write(rk806, BUCK1_VSEL_CTR_SEL + i, CTR_BY_PWRCTRL1);
} else {
for (i = RK806_ID_DCDC1; i < RK806_ID_END; i++) {
if (pdata->dvs_control_suspend[i] == CTR_BY_PWRCTRL1) {
chip_ver = rk806_field_read(rk806, CHIP_VER);
if (chip_ver & 0x08)
rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_SLP_FUN);
else
rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_DVS_FUN);
}
if (pdata->dvs_control_suspend[i] == CTR_BY_PWRCTRL2)
rk806_field_write(rk806, PWRCTRL2_FUN, PWRCTRL_DVS_FUN);
if (pdata->dvs_control_suspend[i] == CTR_BY_PWRCTRL3)
rk806_field_write(rk806, PWRCTRL3_FUN, PWRCTRL_DVS_FUN);
}
for (i = 0; i <= RK806_ID_PLDO6 - RK806_ID_PLDO1; i++) {
value = rk806_field_read(rk806, PLDO1_ON_VSEL + i);
rk806_field_write(rk806, PLDO1_SLP_VSEL + i, value);
@@ -1209,18 +1223,6 @@ static int __maybe_unused rk806_suspend(struct device *dev)
rk806_field_write(rk806, PLDO4_VSEL_CTR_SEL, pdata->dvs_control_suspend[RK806_ID_PLDO3]);
rk806_field_write(rk806, PLDO5_VSEL_CTR_SEL, pdata->dvs_control_suspend[RK806_ID_PLDO4]);
rk806_field_write(rk806, PLDO6_VSEL_CTR_SEL, pdata->dvs_control_suspend[RK806_ID_PLDO5]);
for (i = RK806_ID_DCDC1; i < RK806_ID_END; i++) {
if (pdata->dvs_control_suspend[i] == CTR_BY_PWRCTRL2)
rk806_field_write(rk806, PWRCTRL2_FUN, PWRCTRL_DVS_FUN);
if (pdata->dvs_control_suspend[i] == CTR_BY_PWRCTRL3)
rk806_field_write(rk806, PWRCTRL3_FUN, PWRCTRL_DVS_FUN);
}
chip_ver = rk806_field_read(rk806, CHIP_VER);
if (chip_ver & 0x08)
rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_SLP_FUN);
else
rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_DVS_FUN);
}
return 0;