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ARM64: dts: rk3399: fix enable incorrect HCLK_I2Sx when startup
This patch like below:
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commit 3860aa1ccf
Author: Heiko Stuebner <heiko@sntech.de>
Date: Sat Jan 9 03:18:51 2016 +0100
ARM: dts: rockchip: swap i2s clock ordering on rk3036
For sound setups using the simple-card mechanism, the main clock
(sysclk) is expected to be the first element. For the i2s-driver
itself it doesn't matter, as it uses named clocks, so we can just
swap them.
----
If we set HCLK_I2Sx at first, rockchip_i2s_set_sysclk will set the
HCLK_I2S freq (from example is 100MHz) to set the i2s_div, it is
incorrect.
Change-Id: I2b424ded3845b8ccd3ef233e43c5f9f915544547
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
@@ -917,8 +917,8 @@
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac_bus 7>;
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dma-names = "tx";
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clock-names = "hclk", "mclk";
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clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
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clock-names = "mclk", "hclk";
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clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
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pinctrl-names = "default";
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pinctrl-0 = <&spdif_bus>;
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status = "disabled";
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@@ -932,8 +932,8 @@
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#size-cells = <0>;
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dmas = <&dmac_bus 0>, <&dmac_bus 1>;
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dma-names = "tx", "rx";
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clock-names = "i2s_hclk", "i2s_clk";
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clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_8ch_bus>;
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status = "disabled";
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@@ -947,8 +947,8 @@
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#size-cells = <0>;
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dmas = <&dmac_bus 2>, <&dmac_bus 3>;
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dma-names = "tx", "rx";
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clock-names = "i2s_hclk", "i2s_clk";
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clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_2ch_bus>;
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status = "disabled";
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@@ -962,8 +962,8 @@
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#size-cells = <0>;
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dmas = <&dmac_bus 4>, <&dmac_bus 5>;
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dma-names = "tx", "rx";
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clock-names = "i2s_hclk", "i2s_clk";
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clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
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status = "disabled";
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};
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