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UPSTREAM: clk: rockchip: fix warning reported by kernel-doc
./scripts/kernel-doc -man -v drivers/clk/rockchip/clk.h > /dev/null drivers/clk/rockchip/clk.h:133: warning: missing initial short description on line: * struct rockchip_clk_provider: information about clock provider drivers/clk/rockchip/clk.h:133: info: Scanning doc for struct drivers/clk/rockchip/clk.h:164: warning: missing initial short description on line: * struct rockchip_pll_clock: information about pll clock drivers/clk/rockchip/clk.h:164: info: Scanning doc for struct drivers/clk/rockchip/clk.h:194: warning: No description found for parameter 'parent_names' drivers/clk/rockchip/clk.h:194: warning: No description found for parameter 'num_parents' drivers/clk/rockchip/clk.h:194: warning: Excess struct/union/enum/typedef member 'parent_name' description in 'rockchip_pll_clock' drivers/clk/rockchip/clk.h:235: warning: missing initial short description on line: * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> (cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next commit 1c908b320055e1ce706e91121dbb2ce7934c788f) Change-Id: I18dbd45ebd528fe2a871c98a1561dd0c0bf41e13 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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@@ -121,7 +121,7 @@ enum rockchip_pll_type {
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}
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/**
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* struct rockchip_clk_provider: information about clock provider
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* struct rockchip_clk_provider - information about clock provider
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* @reg_base: virtual address for the register base.
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* @clk_data: holds clock related data like clk* and number of clocks.
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* @cru_node: device-node of the clock-provider
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@@ -152,10 +152,11 @@ struct rockchip_pll_rate_table {
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};
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/**
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* struct rockchip_pll_clock: information about pll clock
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* struct rockchip_pll_clock - information about pll clock
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* @id: platform specific id of the clock.
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* @name: name of this pll clock.
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* @parent_name: name of the parent clock.
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* @parent_names: name of the parent clock.
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* @num_parents: number of parents
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* @flags: optional flags for basic clock.
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* @con_offset: offset of the register for configuring the PLL.
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* @mode_offset: offset of the register for configuring the PLL-mode.
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@@ -223,7 +224,7 @@ struct rockchip_cpuclk_rate_table {
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};
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/**
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* struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
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* struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock
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* @core_reg: register offset of the core settings register
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* @div_core_shift: core divider offset used to divide the pll value
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* @div_core_mask: core divider mask
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