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ASoC: rockchip: rk817-codec: fix pop from DAC_DIG_CLK_DIS and DAC_DIG_CLK_EN

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Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Change-Id: Idfa31a4f3484f1641ebcf46d237244e98e378e93
This commit is contained in:
Binyuan Lan
2024-01-23 13:20:18 +00:00
committed by Tao Huang
parent 2424e1c910
commit fbdf3d8d03
1 changed files with 94 additions and 48 deletions
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142
sound/soc/codecs/rk817_codec.c
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@@ -238,16 +238,22 @@ static int rk817_codec_ctl_gpio(struct rk817_codec_priv *rk817,
{
if ((gpio & CODEC_SET_SPK) &&
rk817->spk_ctl_gpio) {
if (level && rk817->spk_mute_delay)
msleep(rk817->spk_mute_delay);
gpiod_set_value(rk817->spk_ctl_gpio, level);
DBG("%s set spk clt %d\n", __func__, level);
msleep(rk817->spk_mute_delay);
if (!level && rk817->spk_mute_delay)
msleep(rk817->spk_mute_delay);
}
if ((gpio & CODEC_SET_HP) &&
rk817->hp_ctl_gpio) {
if (level && rk817->hp_mute_delay)
msleep(rk817->hp_mute_delay);
gpiod_set_value(rk817->hp_ctl_gpio, level);
DBG("%s set hp clt %d\n", __func__, level);
msleep(rk817->hp_mute_delay);
if (!level && rk817->hp_mute_delay)
msleep(rk817->hp_mute_delay);
}
return 0;
@@ -267,12 +273,12 @@ static int rk817_reset(struct snd_soc_component *component)
snd_soc_component_write(component, RK817_CODEC_APLL_CFG5, 0x00);
snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00);
if (rk817->chip_ver <= 0x4) {
DBG("%s (%d): SMIC TudorAG and previous versions\n",
DBG("%s (%d): 0x4 and previous versions\n",
__func__, __LINE__);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95);
} else {
DBG("%s (%d): SMIC TudorAG version later\n",
DBG("%s (%d): 0x4 version later\n",
__func__, __LINE__);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
@@ -282,6 +288,77 @@ static int rk817_reset(struct snd_soc_component *component)
return 0;
}
static int rk817_restart_dac_digital_clk(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, RK817_CODEC_ADAC_CFG1,
PWD_DACBIAS_MASK, PWD_DACBIAS_DOWN);
usleep_range(500, 600);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS);
usleep_range(500, 600);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN);
DBG("%s: %d - Playback DIG CLK OPS\n", __func__, __LINE__);
usleep_range(500, 600);
snd_soc_component_update_bits(component, RK817_CODEC_ADAC_CFG1,
PWD_DACBIAS_MASK, PWD_DACBIAS_ON);
return 0;
}
static int rk817_restart_dac_digital_clk_and_apll(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, RK817_CODEC_ADAC_CFG1,
PWD_DACBIAS_MASK, PWD_DACBIAS_DOWN);
usleep_range(500, 600);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS);
usleep_range(500, 600);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN);
DBG("%s: %d - Playback DIG CLK OPS\n", __func__, __LINE__);
snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
PLL_PW_DOWN, PLL_PW_DOWN);
usleep_range(50, 60);
snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
PLL_PW_DOWN, PLL_PW_UP);
usleep_range(500, 600);
snd_soc_component_update_bits(component, RK817_CODEC_ADAC_CFG1,
PWD_DACBIAS_MASK, PWD_DACBIAS_ON);
return 0;
}
static int rk817_restart_adc_digital_clk(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
ADC_DIG_CLK_MASK, ADC_DIG_CLK_DIS);
usleep_range(500, 600);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
ADC_DIG_CLK_MASK, ADC_DIG_CLK_EN);
DBG("%s: %d - Capture DIG CLK OPS\n", __func__, __LINE__);
return 0;
}
static int rk817_restart_adc_digital_clk_and_apll(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
ADC_DIG_CLK_MASK, ADC_DIG_CLK_DIS);
usleep_range(500, 600);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
ADC_DIG_CLK_MASK, ADC_DIG_CLK_EN);
DBG("%s: %d - Capture DIG CLK OPS\n", __func__, __LINE__);
snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
PLL_PW_DOWN, PLL_PW_DOWN);
usleep_range(50, 60);
snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
PLL_PW_DOWN, PLL_PW_UP);
usleep_range(500, 600);
return 0;
}
static struct rk817_reg_val_typ playback_power_up_list[] = {
{RK817_CODEC_AREF_RTCFG1, 0x40},
{RK817_CODEC_DDAC_POPD_DACST, 0x02},
@@ -380,22 +457,16 @@ static int rk817_codec_power_up(struct snd_soc_component *component, int type)
/* configure APLL CFG0/4 */
if (rk817->chip_ver <= 0x4) {
DBG("%s (%d): SMIC TudorAG and previous versions\n",
DBG("%s (%d): 0x4 and previous versions\n",
__func__, __LINE__);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95);
} else {
DBG("%s: SMIC TudorAG version later\n", __func__);
DBG("%s: 0x4 version later\n", __func__);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
}
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS);
usleep_range(2000, 2500);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN);
DBG("%s: %d - Playback DIG CLK OPS\n", __func__, __LINE__);
rk817_restart_dac_digital_clk(component);
}
if (type & RK817_CODEC_CAPTURE) {
@@ -411,22 +482,17 @@ static int rk817_codec_power_up(struct snd_soc_component *component, int type)
/* configure APLL CFG0/4 */
if (rk817->chip_ver <= 0x4) {
DBG("%s (%d): SMIC TudorAG and previous versions\n",
DBG("%s (%d): 0x4 and previous versions\n",
__func__, __LINE__);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95);
} else {
DBG("%s: SMIC TudorAG version later\n", __func__);
DBG("%s: 0x4 version later\n", __func__);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
}
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
ADC_DIG_CLK_MASK, ADC_DIG_CLK_DIS);
usleep_range(2000, 2500);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
ADC_DIG_CLK_MASK, ADC_DIG_CLK_EN);
DBG("%s: %d - Capture DIG CLK OPS\n", __func__, __LINE__);
rk817_restart_adc_digital_clk(component);
if (rk817->mic_in_differential)
snd_soc_component_update_bits(component,
@@ -948,25 +1014,19 @@ static int rk817_hw_params(struct snd_pcm_substream *substream,
unsigned int rate = params_rate(params);
unsigned char apll_cfg3_val;
unsigned char dtop_digen_sr_lmt0;
unsigned char dtop_digen_clke;
DBG("%s : sample rate = %dHz\n", __func__, rate);
if (rk817->chip_ver <= 0x4) {
DBG("%s: SMIC TudorAG and previous versions\n", __func__);
DBG("%s: 0x4 and previous versions\n", __func__);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95);
} else {
DBG("%s: SMIC TudorAG version later\n", __func__);
DBG("%s: 0x4 version later\n", __func__);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dtop_digen_clke = DAC_DIG_CLK_EN;
else
dtop_digen_clke = ADC_DIG_CLK_EN;
switch (rate) {
case 8000:
apll_cfg3_val = 0x03;
@@ -998,19 +1058,12 @@ static int rk817_hw_params(struct snd_pcm_substream *substream,
*/
if (!((substream->stream == SNDRV_PCM_STREAM_CAPTURE) && rk817->pdmdata_out_enable)) {
snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, apll_cfg3_val);
/* The 0x00 contains ADC_DIG_CLK_DIS and DAC_DIG_CLK_DIS */
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
dtop_digen_clke, 0x00);
snd_soc_component_update_bits(component, RK817_CODEC_DDAC_SR_LMT0,
DACSRT_MASK, dtop_digen_sr_lmt0);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
dtop_digen_clke, dtop_digen_clke);
snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
PLL_PW_DOWN, PLL_PW_DOWN);
usleep_range(50, 60);
snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
PLL_PW_DOWN, PLL_PW_UP);
usleep_range(500, 600);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
rk817_restart_dac_digital_clk_and_apll(component);
else
rk817_restart_adc_digital_clk_and_apll(component);
}
switch (params_format(params)) {
@@ -1048,14 +1101,7 @@ static int rk817_digital_mute_dac(struct snd_soc_dai *dai, int mute, int stream)
snd_soc_component_update_bits(component,
RK817_CODEC_DDAC_MUTE_MIXCTL,
DACMT_ENABLE, DACMT_ENABLE);
snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
PWD_DACBIAS_DOWN | PWD_DACD_DOWN |
PWD_DACL_DOWN | PWD_DACR_DOWN);
/* Reset DAC DTOP_DIGEN_CLKE for playback stopped */
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_EN, DAC_DIG_CLK_DIS);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
DAC_DIG_CLK_EN, DAC_DIG_CLK_EN);
rk817_restart_dac_digital_clk(component);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
I2SRX_EN_MASK, I2SRX_DIS);
} else {