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media: i2c: techpoint: add tp9951 driver
Signed-off-by: LongChang Ma <chad.ma@rock-chips.com> Change-Id: Ieee236964b12d2dc54c622641463e3bbd90c2ca6
This commit is contained in:
LongChang Ma
@@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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techpoint-objs += techpoint_v4l2.o techpoint_dev.o \
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techpoint_tp9930.o techpoint_tp2855.o \
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techpoint_tp9950.o
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techpoint_tp9950.o techpoint_tp9951.o
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obj-$(CONFIG_VIDEO_TECHPOINT) += techpoint.o
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@@ -52,6 +52,7 @@ enum techpoint_chips {
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CHIP_TP2815,
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CHIP_TP9930,
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CHIP_TP9950,
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CHIP_TP9951,
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};
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enum techpoint_input_type {
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@@ -12,6 +12,7 @@
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#include "techpoint_tp9950.h"
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#include "techpoint_tp2855.h"
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#include "techpoint_tp2815.h"
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#include "techpoint_tp9951.h"
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static DEFINE_MUTEX(reg_sem);
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@@ -99,33 +100,40 @@ static int check_chip_id(struct techpoint *techpoint)
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techpoint_read_reg(client, CHIP_ID_L_REG, &chip_id_l);
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dev_err(dev, "chip_id_h:0x%2x chip_id_l:0x%2x\n", chip_id_h, chip_id_l);
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if (chip_id_h == TP9930_CHIP_ID_H_VALUE &&
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chip_id_l == TP9930_CHIP_ID_L_VALUE) {
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chip_id_l == TP9930_CHIP_ID_L_VALUE) { //tp2832
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dev_info(&client->dev,
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"techpoint check chip id CHIP_TP9930 !\n");
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techpoint->chip_id = CHIP_TP9930;
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techpoint->input_type = TECHPOINT_DVP_BT1120;
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return 0;
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} else if (chip_id_h == TP2855_CHIP_ID_H_VALUE &&
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chip_id_l == TP2855_CHIP_ID_L_VALUE) {
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chip_id_l == TP2855_CHIP_ID_L_VALUE) { //tp2855
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dev_info(&client->dev,
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"techpoint check chip id CHIP_TP2855 !\n");
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techpoint->chip_id = CHIP_TP2855;
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techpoint->input_type = TECHPOINT_MIPI;
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return 0;
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} else if (chip_id_h == TP2815_CHIP_ID_H_VALUE &&
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chip_id_l == TP2815_CHIP_ID_L_VALUE) {
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chip_id_l == TP2815_CHIP_ID_L_VALUE) { //tp2815
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dev_info(&client->dev,
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"techpoint check chip id CHIP_TP2815 !\n");
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techpoint->chip_id = CHIP_TP2855;
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techpoint->input_type = TECHPOINT_MIPI;
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return 0;
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} else if (chip_id_h == TP9950_CHIP_ID_H_VALUE &&
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chip_id_l == TP9950_CHIP_ID_L_VALUE) {
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chip_id_l == TP9950_CHIP_ID_L_VALUE) { //tp2850
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dev_info(&client->dev,
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"techpoint check chip id CHIP_TP9950 !\n");
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techpoint->chip_id = CHIP_TP9950;
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techpoint->input_type = TECHPOINT_MIPI;
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return 0;
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} else if (chip_id_h == TP9951_CHIP_ID_H_VALUE &&
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chip_id_l == TP9951_CHIP_ID_L_VALUE) { //tp2860
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dev_info(&client->dev,
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"techpoint check chip id CHIP_TP9951 !\n");
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techpoint->chip_id = CHIP_TP9951;
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techpoint->input_type = TECHPOINT_MIPI;
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return 0;
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}
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dev_info(&client->dev, "techpoint check chip id failed !\n");
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@@ -143,6 +151,8 @@ int techpoint_initialize_devices(struct techpoint *techpoint)
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tp2855_initialize(techpoint);
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else if (techpoint->chip_id == CHIP_TP9950)
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tp9950_initialize(techpoint);
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else if (techpoint->chip_id == CHIP_TP9951)
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tp9951_initialize(techpoint);
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return 0;
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}
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@@ -185,6 +195,10 @@ static int detect_thread_function(void *data)
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detect_status =
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tp2855_get_channel_input_status
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(techpoint, i);
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else if (techpoint->chip_id == CHIP_TP9951)
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detect_status =
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tp9951_get_channel_input_status
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(techpoint, i);
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if (techpoint->detect_status[i] !=
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detect_status) {
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@@ -202,8 +216,7 @@ static int detect_thread_function(void *data)
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else if (techpoint->chip_id == CHIP_TP2855)
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tp2855_set_decoder_mode(client, i, detect_status);
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techpoint->detect_status[i] =
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detect_status;
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techpoint->detect_status[i] = detect_status;
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need_reset_wait = 5;
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}
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}
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@@ -273,6 +286,11 @@ static __maybe_unused int auto_detect_channel_fmt(struct techpoint *techpoint)
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tp9950_set_channel_reso(client, 0, reso);
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}
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if (techpoint->chip_id == CHIP_TP9951) {
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reso = tp9951_get_channel_reso(client, 0);
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tp9951_set_channel_reso(client, 0, reso);
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}
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mutex_unlock(®_sem);
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return 0;
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638
drivers/media/i2c/techpoint/techpoint_tp9951.c
Normal file
638
drivers/media/i2c/techpoint/techpoint_tp9951.c
Normal file
@@ -0,0 +1,638 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* techpoint lib
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*
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* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
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*/
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#include "techpoint_tp9951.h"
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#include "techpoint_dev.h"
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static struct techpoint_video_modes supported_modes[] = {
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#if TP9951_DEF_PAL
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{
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.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
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.width = 960,
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.height = 576,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_148M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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.bpp = TP9951_BITS_PER_SAMPLE,
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.lane = TP9951_LANES,
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.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
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.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
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.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
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.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
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},
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#endif
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#if TP9951_DEF_NTSC
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{
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.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
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.width = 960,
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.height = 480,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_148M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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.bpp = TP9951_BITS_PER_SAMPLE,
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.lane = TP9951_LANES,
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.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
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.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
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.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
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.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
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},
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#endif
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#if TP9951_DEF_1080P
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{
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.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
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.width = 1920,
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.height = 1080,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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// .link_freq_value = TP9951_LINK_FREQ_594M,
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.link_freq_value = TP9951_LINK_FREQ_297M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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.bpp = TP9951_BITS_PER_SAMPLE,
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.lane = TP9951_LANES,
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.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
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.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
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.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
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.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
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},
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#endif
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#if TP9951_DEF_720P
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{
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.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
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.width = 1280,
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.height = 720,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_297M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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.bpp = TP9951_BITS_PER_SAMPLE,
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.lane = TP9951_LANES,
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.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
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.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
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.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
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.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
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},
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#endif
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};
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int tp9951_initialize(struct techpoint *techpoint)
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{
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int array_size = 0;
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struct i2c_client *client = techpoint->client;
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struct device *dev = &client->dev;
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techpoint->video_modes_num = ARRAY_SIZE(supported_modes);
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array_size =
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sizeof(struct techpoint_video_modes) * techpoint->video_modes_num;
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techpoint->video_modes = devm_kzalloc(dev, array_size, GFP_KERNEL);
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memcpy(techpoint->video_modes, supported_modes, array_size);
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techpoint->cur_video_mode = &techpoint->video_modes[0];
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return 0;
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}
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int tp9951_get_channel_input_status(struct techpoint *techpoint, u8 ch)
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{
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u8 val = 0;
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struct i2c_client *client = techpoint->client;
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if (ch != 0) // tp9951 just support 1 chn
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return 0;
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techpoint_write_reg(client, PAGE_REG, ch);
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techpoint_read_reg(client, INPUT_STATUS_REG, &val);
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dev_dbg(&client->dev, "input_status ch %d : %x\n", ch, val);
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return (val & INPUT_STATUS_MASK) ? 0 : 1;
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}
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int tp9951_get_all_input_status(struct techpoint *techpoint, u8 *detect_status)
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{
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u8 val = 0;
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struct i2c_client *client = techpoint->client;
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// tp9951 just support 1 chn
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techpoint_write_reg(client, PAGE_REG, 0);
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techpoint_read_reg(client, INPUT_STATUS_REG, &val);
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detect_status[0] = tp9951_get_channel_input_status(techpoint, 0);
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return 0;
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}
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static void tp9951_set_mipi_out(struct i2c_client *client,
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enum techpoint_support_reso reso,
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unsigned char lane)
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{
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u8 tmp;
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//mipi setting
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techpoint_write_reg(client, 0x40, 0x08); //select MIPI page
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techpoint_write_reg(client, 0x02, 0x7d);
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techpoint_write_reg(client, 0x03, 0x75);
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techpoint_write_reg(client, 0x04, 0x75);
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techpoint_write_reg(client, 0x13, 0xef);
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techpoint_write_reg(client, 0x20, 0x00);
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techpoint_write_reg(client, 0x23, 0x9e);
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if (lane == MIPI_1LANE) {
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techpoint_write_reg(client, 0x21, 0x11);
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if (TECHPOINT_S_RESO_1080P_30 == reso || TECHPOINT_S_RESO_1080P_25 == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x00);
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techpoint_write_reg(client, 0x15, 0x02);
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techpoint_write_reg(client, 0x2a, 0x08);
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techpoint_write_reg(client, 0x2b, 0x06);
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techpoint_write_reg(client, 0x2c, 0x12);
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techpoint_write_reg(client, 0x2e, 0x0a);
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} else if (TECHPOINT_S_RESO_720P_30 == reso || TECHPOINT_S_RESO_720P_25 == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x00);
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techpoint_write_reg(client, 0x15, 0x12);
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techpoint_write_reg(client, 0x2a, 0x04);
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techpoint_write_reg(client, 0x2b, 0x03);
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techpoint_write_reg(client, 0x2c, 0x0a);
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techpoint_write_reg(client, 0x2e, 0x02);
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} else if (TECHPOINT_S_RESO_NTSC == reso || TECHPOINT_S_RESO_PAL == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x51);
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techpoint_write_reg(client, 0x15, 0x07);
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techpoint_write_reg(client, 0x2a, 0x02);
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techpoint_write_reg(client, 0x2b, 0x01);
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techpoint_write_reg(client, 0x2c, 0x06);
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techpoint_write_reg(client, 0x2e, 0x02);
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}
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} else { // 2 lane
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techpoint_write_reg(client, 0x21, 0x12);
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if (TECHPOINT_S_RESO_1080P_30 == reso || TECHPOINT_S_RESO_1080P_25 == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x41);
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techpoint_write_reg(client, 0x15, 0x02);
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techpoint_write_reg(client, 0x2a, 0x04);
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techpoint_write_reg(client, 0x2b, 0x03);
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techpoint_write_reg(client, 0x2c, 0x0a);
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techpoint_write_reg(client, 0x2e, 0x02);
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} else if (TECHPOINT_S_RESO_720P_30 == reso || TECHPOINT_S_RESO_720P_25 == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x41);
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techpoint_write_reg(client, 0x15, 0x12);
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techpoint_write_reg(client, 0x2a, 0x02);
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techpoint_write_reg(client, 0x2b, 0x01);
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techpoint_write_reg(client, 0x2c, 0x06);
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techpoint_write_reg(client, 0x2e, 0x02);
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} else if (TECHPOINT_S_RESO_NTSC == reso || TECHPOINT_S_RESO_PAL == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x62);
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techpoint_write_reg(client, 0x15, 0x07);
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techpoint_write_reg(client, 0x2a, 0x02);
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techpoint_write_reg(client, 0x2b, 0x00);
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techpoint_write_reg(client, 0x2c, 0x04);
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techpoint_write_reg(client, 0x2e, 0x02);
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}
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}
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techpoint_write_reg(client, 0x40, 0x00); //back to decoder page
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techpoint_read_reg(client, 0x06, &tmp); //PLL reset
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techpoint_write_reg(client, 0x06, 0x80 | tmp);
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techpoint_write_reg(client, 0x40, 0x08); //back to mipi page
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techpoint_read_reg(client, 0x14, &tmp); //PLL reset
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techpoint_write_reg(client, 0x14, 0x80 | tmp);
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techpoint_write_reg(client, 0x14, tmp);
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/* Enable MIPI CSI2 output */
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techpoint_write_reg(client, 0x28, 0x02); //stream off
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techpoint_write_reg(client, 0x28, 0x00); //stream on
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techpoint_write_reg(client, 0x40, 0x00); //back to decoder page
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}
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int tp9951_set_channel_reso(struct i2c_client *client, int ch,
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enum techpoint_support_reso reso)
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{
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int val = reso;
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dev_info(&client->dev, "##$$ %s", __func__);
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techpoint_write_reg(client, 0x40, 0x00); //select decoder page
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techpoint_write_reg(client, 0x06, 0x12); //default value
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techpoint_write_reg(client, 0x42, 0x00); //common setting for all format
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techpoint_write_reg(client, 0x4e, 0x00); //common setting for MIPI output
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techpoint_write_reg(client, 0x54, 0x00); //common setting for MIPI output
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techpoint_write_reg(client, 0x41, ch); //video MUX select
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switch (val) {
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case TECHPOINT_S_RESO_720P_25:
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#if TP9951_DEF_720P
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default:
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#endif
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dev_err(&client->dev, "set channel 720P_25\n");
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techpoint_write_reg(client, 0x02, 0x42);
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techpoint_write_reg(client, 0x07, 0xc0);
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techpoint_write_reg(client, 0x0b, 0xc0);
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techpoint_write_reg(client, 0x0c, 0x13);
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techpoint_write_reg(client, 0x0d, 0x50);
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techpoint_write_reg(client, 0x15, 0x13);
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techpoint_write_reg(client, 0x16, 0x15);
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techpoint_write_reg(client, 0x17, 0x00);
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techpoint_write_reg(client, 0x18, 0x19);
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techpoint_write_reg(client, 0x19, 0xd0);
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techpoint_write_reg(client, 0x1a, 0x25);
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techpoint_write_reg(client, 0x1c, 0x07);//1280*720, 25fps
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techpoint_write_reg(client, 0x1d, 0xbc);//1280*720, 25fps
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techpoint_write_reg(client, 0x20, 0x30);
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||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x60);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x30);
|
||||
techpoint_write_reg(client, 0x2e, 0x70);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x48);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x2e);
|
||||
techpoint_write_reg(client, 0x33, 0x90);
|
||||
techpoint_write_reg(client, 0x35, 0x25);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x18);
|
||||
if (STD_HDA) {
|
||||
techpoint_write_reg(client, 0x02, 0x46);
|
||||
techpoint_write_reg(client, 0x0d, 0x71);
|
||||
techpoint_write_reg(client, 0x18, 0x1b);
|
||||
techpoint_write_reg(client, 0x20, 0x40);
|
||||
techpoint_write_reg(client, 0x21, 0x46);
|
||||
techpoint_write_reg(client, 0x25, 0xfe);
|
||||
techpoint_write_reg(client, 0x26, 0x01);
|
||||
techpoint_write_reg(client, 0x2c, 0x3a);
|
||||
techpoint_write_reg(client, 0x2d, 0x5a);
|
||||
techpoint_write_reg(client, 0x2e, 0x40);
|
||||
techpoint_write_reg(client, 0x30, 0x9e);
|
||||
techpoint_write_reg(client, 0x31, 0x20);
|
||||
techpoint_write_reg(client, 0x32, 0x10);
|
||||
techpoint_write_reg(client, 0x33, 0x90);
|
||||
}
|
||||
|
||||
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
||||
|
||||
break;
|
||||
case TECHPOINT_S_RESO_1080P_25: // FHD25
|
||||
#if TP9951_DEF_1080P
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "set channel 1080P_25\n");
|
||||
techpoint_write_reg(client, 0x02, 0x40);
|
||||
techpoint_write_reg(client, 0x07, 0xc0);
|
||||
techpoint_write_reg(client, 0x0b, 0xc0);
|
||||
techpoint_write_reg(client, 0x0c, 0x03);
|
||||
techpoint_write_reg(client, 0x0d, 0x50);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x03);
|
||||
techpoint_write_reg(client, 0x16, 0xd2);
|
||||
techpoint_write_reg(client, 0x17, 0x80);
|
||||
techpoint_write_reg(client, 0x18, 0x29);
|
||||
techpoint_write_reg(client, 0x19, 0x38);
|
||||
techpoint_write_reg(client, 0x1a, 0x47);
|
||||
techpoint_write_reg(client, 0x1c, 0x0a);//1920*1080, 25fps
|
||||
techpoint_write_reg(client, 0x1d, 0x50);//
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x30);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x60);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x30);
|
||||
techpoint_write_reg(client, 0x2e, 0x70);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x48);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x2e);
|
||||
techpoint_write_reg(client, 0x33, 0x90);
|
||||
techpoint_write_reg(client, 0x35, 0x05);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x1C);
|
||||
if (STD_HDA) {
|
||||
techpoint_write_reg(client, 0x02, 0x44);
|
||||
techpoint_write_reg(client, 0x0d, 0x73);
|
||||
techpoint_write_reg(client, 0x15, 0x01);
|
||||
techpoint_write_reg(client, 0x16, 0xf0);
|
||||
techpoint_write_reg(client, 0x18, 0x2a);
|
||||
techpoint_write_reg(client, 0x20, 0x3c);
|
||||
techpoint_write_reg(client, 0x21, 0x46);
|
||||
techpoint_write_reg(client, 0x25, 0xfe);
|
||||
techpoint_write_reg(client, 0x26, 0x0d);
|
||||
techpoint_write_reg(client, 0x2c, 0x3a);
|
||||
techpoint_write_reg(client, 0x2d, 0x54);
|
||||
techpoint_write_reg(client, 0x2e, 0x40);
|
||||
techpoint_write_reg(client, 0x30, 0xa5);
|
||||
techpoint_write_reg(client, 0x31, 0x86);
|
||||
techpoint_write_reg(client, 0x32, 0xfb);
|
||||
techpoint_write_reg(client, 0x33, 0x60);
|
||||
}
|
||||
|
||||
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
||||
|
||||
break;
|
||||
case TECHPOINT_S_RESO_1080P_30: // FHD30
|
||||
dev_err(&client->dev, "set channel PAL\n");
|
||||
techpoint_write_reg(client, 0x02, 0x40);
|
||||
techpoint_write_reg(client, 0x07, 0xc0);
|
||||
techpoint_write_reg(client, 0x0b, 0xc0);
|
||||
techpoint_write_reg(client, 0x0c, 0x03);
|
||||
techpoint_write_reg(client, 0x0d, 0x50);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x03);
|
||||
techpoint_write_reg(client, 0x16, 0xd2);
|
||||
techpoint_write_reg(client, 0x17, 0x80);
|
||||
techpoint_write_reg(client, 0x18, 0x29);
|
||||
techpoint_write_reg(client, 0x19, 0x38);
|
||||
techpoint_write_reg(client, 0x1a, 0x47);
|
||||
techpoint_write_reg(client, 0x1c, 0x08); //1920*1080, 30fps
|
||||
techpoint_write_reg(client, 0x1d, 0x98); //
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x30);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x60);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x30);
|
||||
techpoint_write_reg(client, 0x2e, 0x70);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x48);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x2e);
|
||||
techpoint_write_reg(client, 0x33, 0x90);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x05);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x1C);
|
||||
|
||||
if (STD_HDA) { //AHD1080p30 extra
|
||||
techpoint_write_reg(client, 0x02, 0x44);
|
||||
techpoint_write_reg(client, 0x0d, 0x72);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x01);
|
||||
techpoint_write_reg(client, 0x16, 0xf0);
|
||||
techpoint_write_reg(client, 0x18, 0x2a);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x38);
|
||||
techpoint_write_reg(client, 0x21, 0x46);
|
||||
|
||||
techpoint_write_reg(client, 0x25, 0xfe);
|
||||
techpoint_write_reg(client, 0x26, 0x0d);
|
||||
|
||||
techpoint_write_reg(client, 0x2c, 0x3a);
|
||||
techpoint_write_reg(client, 0x2d, 0x54);
|
||||
techpoint_write_reg(client, 0x2e, 0x40);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0xa5);
|
||||
techpoint_write_reg(client, 0x31, 0x95);
|
||||
techpoint_write_reg(client, 0x32, 0xe0);
|
||||
techpoint_write_reg(client, 0x33, 0x60);
|
||||
}
|
||||
|
||||
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
||||
break;
|
||||
|
||||
case TECHPOINT_S_RESO_PAL:
|
||||
#if TP9951_DEF_PAL
|
||||
default:
|
||||
#endif
|
||||
|
||||
#if CVBS_960H
|
||||
dev_err(&client->dev, "set channel CVBS_960H\n");
|
||||
|
||||
techpoint_write_reg(client, 0x02, 0x47);
|
||||
techpoint_write_reg(client, 0x0c, 0x13);
|
||||
techpoint_write_reg(client, 0x0d, 0x51);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x13);
|
||||
techpoint_write_reg(client, 0x16, 0x76);
|
||||
techpoint_write_reg(client, 0x17, 0x80);
|
||||
techpoint_write_reg(client, 0x18, 0x17);
|
||||
techpoint_write_reg(client, 0x19, 0x20);
|
||||
techpoint_write_reg(client, 0x1a, 0x17);
|
||||
techpoint_write_reg(client, 0x1c, 0x09);
|
||||
techpoint_write_reg(client, 0x1d, 0x48);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x48);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x37);
|
||||
techpoint_write_reg(client, 0x23, 0x3f);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x70);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x64);
|
||||
techpoint_write_reg(client, 0x2e, 0x56);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x7a);
|
||||
techpoint_write_reg(client, 0x31, 0x4a);
|
||||
techpoint_write_reg(client, 0x32, 0x4d);
|
||||
techpoint_write_reg(client, 0x33, 0xf0);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x65);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x04);
|
||||
|
||||
#else //PAL 720H
|
||||
dev_err(&client->dev, "set channel PAL 720H\n");
|
||||
techpoint_write_reg(client, 0x02, 0x47);
|
||||
techpoint_write_reg(client, 0x06, 0x32);
|
||||
techpoint_write_reg(client, 0x0c, 0x13);
|
||||
techpoint_write_reg(client, 0x0d, 0x51);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x03);
|
||||
techpoint_write_reg(client, 0x16, 0xf0);
|
||||
techpoint_write_reg(client, 0x17, 0xa0);
|
||||
techpoint_write_reg(client, 0x18, 0x17);
|
||||
techpoint_write_reg(client, 0x19, 0x20);
|
||||
techpoint_write_reg(client, 0x1a, 0x15);
|
||||
techpoint_write_reg(client, 0x1c, 0x06);
|
||||
techpoint_write_reg(client, 0x1d, 0xc0);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x48);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x37);
|
||||
techpoint_write_reg(client, 0x23, 0x3f);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x70);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x4b);
|
||||
techpoint_write_reg(client, 0x2e, 0x56);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x7a);
|
||||
techpoint_write_reg(client, 0x31, 0x4a);
|
||||
techpoint_write_reg(client, 0x32, 0x4d);
|
||||
techpoint_write_reg(client, 0x33, 0xfb);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x65);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x04);
|
||||
#endif
|
||||
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
||||
|
||||
break;
|
||||
case TECHPOINT_S_RESO_NTSC:
|
||||
#if TP9951_DEF_NTSC
|
||||
default:
|
||||
#endif
|
||||
|
||||
#if CVBS_960H
|
||||
dev_err(&client->dev, "set channel NTSC CVBS_960H\n");
|
||||
techpoint_write_reg(client, 0x02, 0x47);
|
||||
techpoint_write_reg(client, 0x0c, 0x13);
|
||||
techpoint_write_reg(client, 0x0d, 0x50);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x13);
|
||||
techpoint_write_reg(client, 0x16, 0x60);
|
||||
techpoint_write_reg(client, 0x17, 0x80);
|
||||
techpoint_write_reg(client, 0x18, 0x12);
|
||||
techpoint_write_reg(client, 0x19, 0xf0);
|
||||
techpoint_write_reg(client, 0x1a, 0x07);
|
||||
techpoint_write_reg(client, 0x1c, 0x09);
|
||||
techpoint_write_reg(client, 0x1d, 0x38);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x40);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x70);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x68);
|
||||
techpoint_write_reg(client, 0x2e, 0x57);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x62);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x96);
|
||||
techpoint_write_reg(client, 0x33, 0xc0);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x65);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x04);
|
||||
#else
|
||||
dev_err(&client->dev, "set channel NTSC 720H\n");
|
||||
techpoint_write_reg(client, 0x02, 0x47);
|
||||
techpoint_write_reg(client, 0x0c, 0x13);
|
||||
techpoint_write_reg(client, 0x0d, 0x50);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x03);
|
||||
techpoint_write_reg(client, 0x16, 0xd6);
|
||||
techpoint_write_reg(client, 0x17, 0xa0);
|
||||
techpoint_write_reg(client, 0x18, 0x12);
|
||||
techpoint_write_reg(client, 0x19, 0xf0);
|
||||
techpoint_write_reg(client, 0x1a, 0x05);
|
||||
techpoint_write_reg(client, 0x1c, 0x06);
|
||||
techpoint_write_reg(client, 0x1d, 0xb4);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x40);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x70);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x4b);
|
||||
techpoint_write_reg(client, 0x2e, 0x57);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x62);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x96);
|
||||
techpoint_write_reg(client, 0x33, 0xcb);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x65);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x04);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
#if TECHPOINT_TEST_PATTERN
|
||||
techpoint_write_reg(client, 0x2a, 0x3c);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
// detect for reference only, the accuracy may be affected by the current invoked decoding standard.
|
||||
int tp9951_get_channel_reso(struct i2c_client *client, int ch)
|
||||
{
|
||||
u8 detect_fmt = 0xff;
|
||||
u8 reso = 0xff;
|
||||
|
||||
techpoint_write_reg(client, 0x40, ch);
|
||||
techpoint_read_reg(client, 0x03, &detect_fmt);
|
||||
reso = detect_fmt & 0x7;
|
||||
|
||||
switch (reso) {
|
||||
case TP9951_CVSTD_720P_25:
|
||||
#if TP9951_DEF_720P
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "detect channel %d 720P_25\n", ch);
|
||||
return TECHPOINT_S_RESO_720P_25;
|
||||
case TP9951_CVSTD_1080P_25:
|
||||
#if TP9951_DEF_1080P
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "detect channel %d 1080P_25\n", ch);
|
||||
return TECHPOINT_S_RESO_1080P_25;
|
||||
case TP9951_CVSTD_PAL:
|
||||
#if TP9951_DEF_PAL
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "detect channel %d PAL\n", ch);
|
||||
return TECHPOINT_S_RESO_PAL;
|
||||
case TP9951_CVSTD_NTSC:
|
||||
#if TP9951_DEF_NTSC
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "detect channel %d NTSC\n", ch);
|
||||
return TECHPOINT_S_RESO_NTSC;
|
||||
}
|
||||
|
||||
return reso;
|
||||
}
|
||||
|
||||
int tp9951_set_quick_stream(struct i2c_client *client, u32 stream)
|
||||
{
|
||||
// mutex_lock(&techpoint->mutex);
|
||||
if (stream) {
|
||||
techpoint_write_reg(client, 0x40, 0x8);
|
||||
techpoint_write_reg(client, 0x28, 0x0);
|
||||
} else {
|
||||
techpoint_write_reg(client, 0x40, 0x8);
|
||||
techpoint_write_reg(client, 0x28, 0x2);
|
||||
usleep_range(40 * 1000, 50 * 1000);
|
||||
}
|
||||
// mutex_unlock(&techpoint->mutex);
|
||||
return 0;
|
||||
}
|
||||
76
drivers/media/i2c/techpoint/techpoint_tp9951.h
Normal file
76
drivers/media/i2c/techpoint/techpoint_tp9951.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* techpoint tp9951 regs
|
||||
*
|
||||
* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _TECHPOINT_TP9951_H
|
||||
#define _TECHPOINT_TP9951_H
|
||||
|
||||
#include "techpoint_common.h"
|
||||
|
||||
#define DEBUG
|
||||
|
||||
#define TP9951_DEF_1080P 1
|
||||
#define TP9951_DEF_720P 0
|
||||
#define TP9951_DEF_PAL 0
|
||||
#define TP9951_DEF_NTSC 0
|
||||
|
||||
#define STD_TVI 0
|
||||
#define STD_HDA 1
|
||||
|
||||
// device id 0x2860
|
||||
#define TP9951_CHIP_ID_H_REG 0xFE
|
||||
#define TP9951_CHIP_ID_H_VALUE 0x28
|
||||
#define TP9951_CHIP_ID_L_REG 0xFF
|
||||
#define TP9951_CHIP_ID_L_VALUE 0x60
|
||||
|
||||
#define TP9951_LINK_FREQ_148M (148500000UL >> 1)
|
||||
#define TP9951_LINK_FREQ_297M (297000000UL >> 1)
|
||||
#define TP9951_LINK_FREQ_594M (594000000UL >> 1)
|
||||
#define TP9951_LANES 2
|
||||
#define TP9951_BITS_PER_SAMPLE 8
|
||||
|
||||
enum tp9952_support_mipi_lane {
|
||||
MIPI_2LANE,
|
||||
MIPI_1LANE,
|
||||
};
|
||||
|
||||
#define CVBS_960H (0) //1->960H 0->720H
|
||||
|
||||
enum tp9951_support_reso {
|
||||
TP9951_CVSTD_720P_60 = 0,
|
||||
TP9951_CVSTD_720P_50,
|
||||
TP9951_CVSTD_1080P_30,
|
||||
TP9951_CVSTD_1080P_25,
|
||||
TP9951_CVSTD_720P_30,
|
||||
TP9951_CVSTD_720P_25,
|
||||
TP9951_CVSTD_SD,
|
||||
TP9951_CVSTD_OTHER,
|
||||
TP9951_CVSTD_720P_275,
|
||||
TP9951_CVSTD_QHD30, //960×540 only support with 2lane mode
|
||||
TP9951_CVSTD_QHD25, //960×540 only support with 2lane mode
|
||||
TP9951_CVSTD_PAL,
|
||||
TP9951_CVSTD_NTSC,
|
||||
TP9951_CVSTD_UVGA25, //1280x960p25, must use with MIPI_4CH4LANE_445M
|
||||
TP9951_CVSTD_UVGA30, //1280x960p30, must use with MIPI_4CH4LANE_445M
|
||||
TP9951_CVSTD_A_UVGA30, //HDA 1280x960p30, must use with MIPI_4CH4LANE_378M
|
||||
TP9951_CVSTD_F_UVGA30, //FH 1280x960p30, 1800x1000
|
||||
TP9951_CVSTD_HD30864, //total 1600x900 86.4M
|
||||
TP9951_CVSTD_HD30HDR, //special 720p30 with ISX019/SC120AT,total 1650x900
|
||||
TP9951_CVSTD_1080P_60,//only support with 2lane mode
|
||||
TP9951_CVSTD_1080P_50,//only support with 2lane mode
|
||||
TP9951_CVSTD_1080P_28,
|
||||
TP9951_CVSTD_1080P_275,
|
||||
};
|
||||
|
||||
int tp9951_initialize(struct techpoint *techpoint);
|
||||
int tp9951_get_channel_input_status(struct techpoint *techpoint, u8 ch);
|
||||
int tp9951_get_all_input_status(struct techpoint *techpoint, u8 *detect_status);
|
||||
int tp9951_set_channel_reso(struct i2c_client *client, int ch,
|
||||
enum techpoint_support_reso reso);
|
||||
int tp9951_get_channel_reso(struct i2c_client *client, int ch);
|
||||
int tp9951_set_quick_stream(struct i2c_client *client, u32 stream);
|
||||
|
||||
#endif // _TECHPOINT_TP9951_H
|
||||
@@ -860,6 +860,7 @@ static const struct of_device_id techpoint_of_match[] = {
|
||||
{ .compatible = "techpoint,tp2815" },
|
||||
{ .compatible = "techpoint,tp9930" },
|
||||
{ .compatible = "techpoint,tp9950" },
|
||||
{ .compatible = "techpoint,tp9951" },
|
||||
{ },
|
||||
};
|
||||
|
||||
@@ -1297,7 +1298,6 @@ static int techpoint_audio_probe(struct techpoint *techpoint)
|
||||
}
|
||||
|
||||
if (techpoint->chip_id == CHIP_TP9930) {
|
||||
|
||||
techpoint_write_reg(techpoint->client, 0x40, 0x00);
|
||||
for (i = 0; i < 0xff; i++)
|
||||
techpoint_write_reg(techpoint->client, i, 0xbb);
|
||||
|
||||
Reference in New Issue
Block a user