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UPSTREAM: arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 fractional version fields

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The naming for fractional versions fields in ID_AA64PFR1_EL1 does not align
with that in the architecture, lacking underscores and using upper case
where the architecture uses lower case. In preparation for automatic
generation of defines bring the code in sync with the architecture, no
functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-18-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit cf7fdbbe83)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 233587962
Bug: 233588291
Change-Id: Ic90b58f3a372547c9faf2a652a9ea018e776b366
This commit is contained in:
Mark Brown
2022-09-05 23:54:14 +01:00
committed by Will Deacon
parent 76eac5d394
commit fd6970e812
2 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/include/asm/sysreg.h
View File

@@ -863,8 +863,8 @@
/* id_aa64pfr1 */
#define ID_AA64PFR1_EL1_SME_SHIFT 24
#define ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
#define ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
#define ID_AA64PFR1_EL1_MPAM_frac_SHIFT 16
#define ID_AA64PFR1_EL1_RAS_frac_SHIFT 12
#define ID_AA64PFR1_EL1_MTE_SHIFT 8
#define ID_AA64PFR1_EL1_SSBS_SHIFT 4
#define ID_AA64PFR1_EL1_BT_SHIFT 0

4
arch/arm64/kernel/cpufeature.c
View File

@@ -264,8 +264,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAMFRAC_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RASFRAC_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI),