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clk: rockchip: px30: Add clock id for aclk_bus_src and aclk_peri_src

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Change-Id: I3467b4f799a6f5402eed3d20e4bd2c02ae30c92f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-02-21 11:22:21 +08:00
committed by Tao Huang
parent d9c3f985e4
commit fda77d7005
2 changed files with 4 additions and 2 deletions
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4
drivers/clk/rockchip/clk-px30.c
View File

@@ -483,7 +483,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
* Clock-Architecture Diagram 7
*/
COMPOSITE_NODIV(0, "aclk_peri_src", mux_gpll_cpll_p, 0,
COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0,
PX30_CLKSEL_CON(14), 15, 1, MFLAGS,
PX30_CLKGATE_CON(5), 7, GFLAGS),
COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
@@ -601,7 +601,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
*/
/* PD_BUS */
COMPOSITE_NODIV(0, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(23), 15, 1, MFLAGS,
PX30_CLKGATE_CON(8), 6, GFLAGS),
COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,

2
include/dt-bindings/clock/px30-cru.h
View File

@@ -119,6 +119,8 @@
#define ACLK_GIC 184
#define ACLK_DCF 186
#define ACLK_DMAC 187
#define ACLK_BUS_SRC 188
#define ACLK_PERI_SRC 189
/* hclk gates */
#define HCLK_BUS_PRE 240