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drm/rockchip: vop3: move cluster mix config from vop_ctrl to cluster_regs

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cluster mix config followed cluster, so we move mix regsiter from
vop_ctrl to cluster_regs is more suitable.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I28d80ce9e902992870b9876296af3daa2f5add65
This commit is contained in:
Sandy Huang
2022-04-28 11:28:18 +08:00
committed by Tao Huang
parent 9a3072f627
commit fdb920eef1
4 changed files with 44 additions and 29 deletions
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9
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -552,6 +552,11 @@ struct vop2_cluster_regs {
struct vop_reg enable;
struct vop_reg afbc_enable;
struct vop_reg lb_mode;
struct vop_reg src_color_ctrl;
struct vop_reg dst_color_ctrl;
struct vop_reg src_alpha_ctrl;
struct vop_reg dst_alpha_ctrl;
};
struct vop2_scl_regs {
@@ -1037,10 +1042,6 @@ struct vop2_ctrl {
struct vop_reg mipi0_ds_mode;
struct vop_reg mipi1_ds_mode;
struct vop_reg cluster0_src_color_ctrl;
struct vop_reg cluster0_dst_color_ctrl;
struct vop_reg cluster0_src_alpha_ctrl;
struct vop_reg cluster0_dst_alpha_ctrl;
struct vop_reg src_color_ctrl;
struct vop_reg dst_color_ctrl;
struct vop_reg src_alpha_ctrl;

22
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -6992,11 +6992,10 @@ static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, uint8_t port_id)
*/
static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_cluster *cluster)
{
uint32_t src_color_ctrl_offset = vop2->data->ctrl->cluster0_src_color_ctrl.offset;
uint32_t dst_color_ctrl_offset = vop2->data->ctrl->cluster0_dst_color_ctrl.offset;
uint32_t src_alpha_ctrl_offset = vop2->data->ctrl->cluster0_src_alpha_ctrl.offset;
uint32_t dst_alpha_ctrl_offset = vop2->data->ctrl->cluster0_dst_alpha_ctrl.offset;
uint32_t offset = (cluster->main->phys_id * 0x10);
uint32_t src_color_ctrl_offset = cluster->main->regs->cluster->src_color_ctrl.offset;
uint32_t dst_color_ctrl_offset = cluster->main->regs->cluster->dst_color_ctrl.offset;
uint32_t src_alpha_ctrl_offset = cluster->main->regs->cluster->src_alpha_ctrl.offset;
uint32_t dst_alpha_ctrl_offset = cluster->main->regs->cluster->dst_alpha_ctrl.offset;
struct drm_framebuffer *fb;
struct vop2_alpha_config alpha_config;
struct vop2_alpha alpha;
@@ -7012,11 +7011,6 @@ static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_cluster *clu
bool premulti_en = false;
bool swap = false;
if (cluster->main->phys_id == ROCKCHIP_VOP2_CLUSTER2)
offset = 0x20;
else if (cluster->main->phys_id == ROCKCHIP_VOP2_CLUSTER3)
offset = 0x30;
if (!sub_win) {
/* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
@@ -7072,10 +7066,10 @@ static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_cluster *clu
vop2_parse_alpha(&alpha_config, &alpha);
alpha.src_color_ctrl.bits.src_dst_swap = swap;
vop2_writel(vop2, src_color_ctrl_offset + offset, alpha.src_color_ctrl.val);
vop2_writel(vop2, dst_color_ctrl_offset + offset, alpha.dst_color_ctrl.val);
vop2_writel(vop2, src_alpha_ctrl_offset + offset, alpha.src_alpha_ctrl.val);
vop2_writel(vop2, dst_alpha_ctrl_offset + offset, alpha.dst_alpha_ctrl.val);
vop2_writel(vop2, src_color_ctrl_offset, alpha.src_color_ctrl.val);
vop2_writel(vop2, dst_color_ctrl_offset, alpha.dst_color_ctrl.val);
vop2_writel(vop2, src_alpha_ctrl_offset, alpha.src_alpha_ctrl.val);
vop2_writel(vop2, dst_alpha_ctrl_offset, alpha.dst_alpha_ctrl.val);
}
static void vop2_setup_alpha(struct vop2_video_port *vp,

30
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1445,28 +1445,44 @@ static const struct vop2_layer_data rk3568_vop_layers[] = {
};
static const struct vop2_cluster_regs rk3568_vop_cluster0 = {
static const struct vop2_cluster_regs rk3568_vop_cluster0 = {
.afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
.lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
.src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
.dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
.src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
.dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
};
static const struct vop2_cluster_regs rk3568_vop_cluster1 = {
static const struct vop2_cluster_regs rk3568_vop_cluster1 = {
.afbc_enable = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 1),
.enable = VOP_REG(RK3568_CLUSTER1_CTRL, 1, 0),
.lb_mode = VOP_REG(RK3568_CLUSTER1_CTRL, 0xf, 4),
.src_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
.dst_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
.src_alpha_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
.dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
};
static const struct vop2_cluster_regs rk3588_vop_cluster2 = {
static const struct vop2_cluster_regs rk3588_vop_cluster2 = {
.afbc_enable = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 1),
.enable = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 0),
.lb_mode = VOP_REG(RK3588_CLUSTER2_CTRL, 0xf, 4),
.src_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
.dst_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
.dst_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
};
static const struct vop2_cluster_regs rk3588_vop_cluster3 = {
.afbc_enable = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 1),
.enable = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 0),
.lb_mode = VOP_REG(RK3588_CLUSTER3_CTRL, 0xf, 4),
.src_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
.dst_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
.dst_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
};
static const struct vop_afbc rk3568_cluster0_afbc = {
@@ -2584,10 +2600,6 @@ static const struct vop2_ctrl rk3568_vop_ctrl = {
.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
.cluster0_src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
.cluster0_dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
.cluster0_src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
.cluster0_dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
.src_color_ctrl = VOP_REG(RK3568_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
.dst_color_ctrl = VOP_REG(RK3568_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
.src_alpha_ctrl = VOP_REG(RK3568_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
@@ -2667,10 +2679,6 @@ static const struct vop2_ctrl rk3588_vop_ctrl = {
.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
.cluster0_src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
.cluster0_dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
.cluster0_src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
.cluster0_dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
.src_color_ctrl = VOP_REG(RK3568_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
.dst_color_ctrl = VOP_REG(RK3568_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
.src_alpha_ctrl = VOP_REG(RK3568_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),

12
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1217,6 +1217,18 @@
#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
#define RK3568_CLUSTER1_MIX_SRC_COLOR_CTRL 0x620
#define RK3568_CLUSTER1_MIX_DST_COLOR_CTRL 0x624
#define RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL 0x628
#define RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL 0x62C
#define RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL 0x630
#define RK3588_CLUSTER2_MIX_DST_COLOR_CTRL 0x634
#define RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL 0x638
#define RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL 0x63C
#define RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL 0x640
#define RK3588_CLUSTER3_MIX_DST_COLOR_CTRL 0x644
#define RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL 0x648
#define RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL 0x64C
#define RK3568_MIX0_SRC_COLOR_CTRL 0x650
#define RK3568_MIX0_DST_COLOR_CTRL 0x654
#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658