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arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0

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The PHY interrupt (INT_N) pin is connected to IRQ0 for ETH0.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230712151153.81965-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
2023-07-12 16:11:53 +01:00
committed by Geert Uytterhoeven
parent 7a98d75c4a
commit fe7297bf01
1 changed files with 5 additions and 1 deletions
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6
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
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@@ -6,6 +6,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
@@ -74,6 +75,8 @@
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
interrupt-parent = <&irqc>;
interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -121,7 +124,8 @@
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */
};
gpio-sd0-pwr-en-hog {