RK3588/RK3576 support max ffe level up to 3, but some TVS
such as samsung Q700T only support level 0. The max ffe
level is optional according to the hdmi specification.
Therefore, the default max ffe level is set to 0 and can
be configured via dts.
Change-Id: I94d56559c2fe38f8dade63c24c7bcdd13a9aefc9
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
To eliminate the following err log when running test_offscreen_glmark2.sh on the 3588 Linux device:
[ 157.846768] mali fb000000.gpu: Invalid activity state transition. (prev_act = 1, cur_act = 1)
This change originally comes from ARM's suggested modifications_from_SP_241012.
Change-Id: I5f70d9deaca76cd14dda073160f2836c6dc83c47
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Base on rk3506_defconfig, the rk3502-robot.config difference are
- remove display/ethernet
- add media/v4l2 subsystem and gc2145 sensor
- enable zram swap
- remove no-in-use configs to shrink Image size, about 4.4MB
The other rk3502 boards can use rk3506_defconfig and it's fragments.
Change-Id: I3517aec9c5c4f5368724e648615a5553cc7ac19b
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
motorcomm 8011AN PHY is not capable of automatically detecting
the VDDIO voltage; therefore, it necessitates initialization
configurations that correspond to actual VDDIO voltage levels.
vddio property designates the PHY's IO voltage.
If the vddio property is not specified in the DTS,
the default 3V3 IO hardware initialization settings will be applied.
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>
Change-Id: Iea056f30d8ad47e5970101b4543cfda6f5c843a9
If dma_object is not used, NULL pointer dereference was found.
Fixes: 52729bfaff ("PCI: rockchip: dw: Move dma_obj initialization into rk_pcie_init_dma_trx()")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I5fe8ec539af1188b5da806026f164a493a577c46
The original configuration will lead to some screen display screen offset,
adjust the dclk delay again to make the compatibility higher
Type: Fix
Redmine ID: N/A
Associated modifications: N/A
Test: N/A
Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I732556b429b49418123fd889b67e26885e9b25f8
It is needed to enable rb swap to support MEDIA_BUS_FMT_BGR888_1X24,
because the default 24bpp rgb output is MEDIA_BUS_FMT_RGB888_1X24.
Change-Id: Ifb55f0e97f3a914b9f66b6de49e85697fdc7aeae
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
According to rk3506 SI report, dclk of bt1120/bt656/rgb need to
be inverted by default, in order to ensure that the data is sampled
along the rising edge.
Change-Id: I734f146b5cb33ac6f7f069509a8bb16adefe12d4
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
When enable dci, dci output color format is yuv full
range. So plane csc input is full range.
If hdr is enable plane overlay is rgb so post-csc
input is full range.
Change-Id: I7f98f48ff1ce129aecefb03c587d629b4aca1a0d
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
In the case of devices like Wi-Fi keep on during the sleep, need to
speed up the PCIe wake-up speed when exiting the lite mode sleep avoid
input event drop.
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Change-Id: I91fc2f9cc79bef0f9ee28b9ed929bfbc19e8a5fd
1.controller aasert
2.phy initial
3.controller deassert for fully release
4.wait for phy lock
Change-Id: Id7d760825936ecf1c721aa18735e49f644150341
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This property is designed for devices like Wi-Fi which keep power
on and keep #PERST low during sleep. So there is no need to wait
long perst inactive time when doing resume.
Add rockchip,s2r-perst-inactive-ms for developers to assign any
value they need.
Change-Id: I373e4b2078958bbadfbc6451b02a93d5a0e60f3c
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The win phy id can be used by dts and vop2 driver, so move them together
at rockchip_vop.h
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I0d6c8d48ba42425ff73d65aef843011d7112d981
RK356x can't support uv swap, so only can support YVYU and VYUY.
Fixes: cf58ab4406 ("drm/rockchip: vop2: rename and correct supported format")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iea986580194b4a2aa6ce9943b27b8b3766285502
solved the problem that the fast startup probability is not displayed
Change-Id: Ib65866467dea93955d1b75389d7ef5790c9bc65d
Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com>
Add bindings for the Rockchip Flexbus controller under SPI mode.
Change-Id: I894bc3f6bcfe62cbe593be2e932bf982aad758fd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Lane event counter usage in Rockchip is slightly different with
T-Head. Fix it by checking vendor ID.
Fixes: 6cb6a00862 ("perf/dwc_pcie: Add support for Rockchip vendor devices")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iccc25bb7b352f73bae963d827f14b2f7405608b2
The rockchip,data-swap can help to swap left and right channel
display data in dual channel mode.
Change-Id: I9da870852421e12477027cb74ee01ee9a951c14f
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Since Rockchip's GPIO hardware debounce function does not support
configuring individual pins, it will not be used.
Partially revert commit 2af76b3213 ("gpio: rockchip: Update debounce config function").
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I3c9fd877643aaac3816181a61052d395c95c6593
During the playback, if PLL_PW_DOWN and PLL_PW_UP is performed,
a POP sound is generated.
When the sample rate does not change, do not restart the pll.
Change-Id: I83de976e6e2752a85c57fbc4d4eb6bd5f1b21fbf
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
