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PCI: dw: rockchip: Modify the initialization timing of phy
1.controller aasert 2.phy initial 3.controller deassert for fully release 4.wait for phy lock Change-Id: Id7d760825936ecf1c721aa18735e49f644150341 Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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@@ -672,8 +672,16 @@ static int rockchip_pcie_init_host(struct rockchip_pcie *rockchip)
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if (ret)
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goto disable_phy;
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ret = phy_calibrate(rockchip->phy);
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if (ret) {
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dev_err(dev, "phy lock failed\n");
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goto disable_controller;
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}
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return 0;
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disable_controller:
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reset_control_assert(rockchip->rst);
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disable_phy:
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phy_exit(rockchip->phy);
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phy_power_off(rockchip->phy);
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@@ -1506,7 +1506,6 @@ static int rk_pcie_really_probe(void *p)
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reset_control_assert(rk_pcie->rsts);
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udelay(10);
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reset_control_deassert(rk_pcie->rsts);
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ret = clk_bulk_prepare_enable(rk_pcie->clk_cnt, rk_pcie->clks);
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if (ret) {
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@@ -1520,6 +1519,14 @@ static int rk_pcie_really_probe(void *p)
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goto disable_clk;
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}
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reset_control_deassert(rk_pcie->rsts);
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ret = phy_calibrate(rk_pcie->phy);
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if (ret) {
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dev_err(dev, "phy lock failed\n");
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goto disable_phy;
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}
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/* 5. host registers manipulation */
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ret = rk_pcie_host_config(rk_pcie);
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if (ret) {
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