PCI: dw: rockchip: Modify the initialization timing of phy

1.controller aasert
2.phy initial
3.controller deassert for fully release
4.wait for phy lock

Change-Id: Id7d760825936ecf1c721aa18735e49f644150341
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2024-10-03 11:18:08 +08:00
committed by Dingqiang Lin
parent 9b20bd8277
commit d8b65faa22
2 changed files with 16 additions and 1 deletions

View File

@@ -672,8 +672,16 @@ static int rockchip_pcie_init_host(struct rockchip_pcie *rockchip)
if (ret)
goto disable_phy;
ret = phy_calibrate(rockchip->phy);
if (ret) {
dev_err(dev, "phy lock failed\n");
goto disable_controller;
}
return 0;
disable_controller:
reset_control_assert(rockchip->rst);
disable_phy:
phy_exit(rockchip->phy);
phy_power_off(rockchip->phy);

View File

@@ -1506,7 +1506,6 @@ static int rk_pcie_really_probe(void *p)
reset_control_assert(rk_pcie->rsts);
udelay(10);
reset_control_deassert(rk_pcie->rsts);
ret = clk_bulk_prepare_enable(rk_pcie->clk_cnt, rk_pcie->clks);
if (ret) {
@@ -1520,6 +1519,14 @@ static int rk_pcie_really_probe(void *p)
goto disable_clk;
}
reset_control_deassert(rk_pcie->rsts);
ret = phy_calibrate(rk_pcie->phy);
if (ret) {
dev_err(dev, "phy lock failed\n");
goto disable_phy;
}
/* 5. host registers manipulation */
ret = rk_pcie_host_config(rk_pcie);
if (ret) {