The functions in mcpm_entry.c are mostly intended for use during
scary cache and coherency disabling sequences, or do other things
which confuse trace ... like powering a CPU down and not
returning. Similarly for the backend code.
For simplicity, this patch just makes whole files notrace.
There should be more than enough traceable points on the paths to
these functions, but we can be more fine-grained later if there is
a need for it.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
This patch allows the vexpress 'rtsm' native backend to probe
the dt for presence of the psci backend. If present then the native
implementation of the 'bL_platform_power_ops' is not used.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Add the required code to properly handle race free platform coherency exit
to the DCSCB power down method.
The power_up_setup callback is used to enable the CCI interface for
the cluster being brought up. This must be done in assembly before
the kernel environment is entered.
Thanks to Achin Gupta and Nicolas Pitre for their help and
contributions.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
If 4 CPUs are assumed, the A15x1-A7x1 model configuration would never
shut down the initial cluster as the 0xf reset bit mask will never be
observed. Let's construct this mask based on the provided information
in the DCSCB config register for the number of CPUs per cluster.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
It is possible for a CPU to be told to power up before it managed
to power itself down. Solve this race with a usage count to deal
with this possibility as mandated by the MCPM API definition.
Signed-off-by: nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
This adds basic CPU and cluster reset controls on RTSM for the
A15x4-A7x4 model configuration using the Dual Cluster System
Configuration Block (DCSCB).
The cache coherency interconnect (CCI) is not handled yet.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
This patch adds the 'psci' kernel command line option. Secure firmware cannot
yet add a psci device node in the dt to indicate whether it supports psci or
not. So in the current dt, the psci device node is present by default. The
probe function will always indicate that the secure firmware implements psci
irrespective of the address space linux runs in as the same device tree will
be used in either case. Hence a kernel cmdline option is required to choose
either the native or psci power api backend depending upon the address space
linux is running in.
Specifying 'psci=enable' in the cmdline will allow Linux running in the
non-secure address space to use the same dt but use the psci backend instead
of the native backend. It effectively overrides the presence of the native
implementation by ensuring registration of the psci backend. Linux running in
the secure address space will use the native backend for power management when
'psci=disable' in the cmdline (also the default value i.e. psci backend is
disabled by default) or the psci node in the dt is absent.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
This patch adds a probe function to check if the secure firmware has an
implementation of the Power State Coordination Interface.
'bL_platform_power_ops' will be implemented by:
a. a native backend when Linux runs in secure world
b. a psci backend which relies on the secure firmware to implement the
power ops
presence of b. will be indicated by the psci device node in the device tree.
The device node is expected to be populated by the secure firmware if it
supports psci. If the native backend detects a psci node then it bails out
allowing the psci backend to be registered.
Also a dummy 'psci_probe' function is added for the case when psci support
is not included. This prevents the build from breaking for tc2 and the
rtsm platforms.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
This patch adds a possible error code of the cpu_on psci api. It
indicates that the cpu specified in the cpu_on call is up and running
(e.g. the firmware still has not seen the preceding cpu_off call).
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
The TC2 versatile express core tile integrates a logic block that provides the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power management. The logic block, called Serial Power Controller
(SPC), contains several memory mapped registers to control among other things
low-power states, operating points and reset control.
This patch provides a driver that enables run-time control of features
implemented by the SPC control logic.
The driver also provides a bridge interface through the vexpress config
infrastructure. Operations allowing to read/write operating points are
made to go via the same interface as configuration transactions so that
all requests to M3 are serialized.
Device tree bindings documentation for the SPC component is provided with
the patchset.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
The introduction of Serial Power Controller (SPC) requires the vexpress
config interface to change slightly since the SPC memory mapped interface
can be used as configuration bus but also for operating points
programming and retrieval. The helper that allocates the bridge functions
requires an additional parameter allowing to request component specific
functions that need not be initialized through device tree bindings but
just using simple look-up and statically defined constants.
This patch introduces the necessary changes to the vexpress config layer
to cater for the new vexpress bridge interface requirements.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Achin Gupta <achin.gupta@arm.com>
Cc: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
CCI400 has a set of counters that can be used to profile different
transations at CCI master and slave interfaces. These counters can
observe different kinds of transations passing through the CCI and
provide a system-level view of activity.
This patch adds support for CCI PMU by extending the existing CCI
driver.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
This is a hack to enable the old CCI PMU patches to be used with the new
CCI driver. The CCI PMU is (mis)represented by a separate node in TC2
device-tree.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
This provides cci_enable_port_for_self(). This is the counterpart to
cci_disable_port_by_cpu(self).
This is meant to be called from the MCPM machine specific power_up_setup
callback code when the appropriate affinity level needs to be initialized.
The code therefore has to be position independent as the MMU is still off
and it cannot rely on any stack space.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Dave Martin <dave.martin@linaro.org>
On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.
This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.
Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.
CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.
Documentation describing the CCI DT bindings is provided with the patch.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
The BIG_LITTLE config option is independent from the MCPM one.
Semantically, they cover different things. MCPM can be used on non
b.L systems for example.
Signed-of-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
The functions in mcpm_entry.c are mostly intended for use during
scary cache and coherency disabling sequences, or do other things
which confuse trace ... like powering a CPU down and not
returning. Similarly for the backend code.
For simplicity, this patch just makes whole files notrace.
There should be more than enough traceable points on the paths to
these functions, but we can be more fine-grained later if there is
a need for it.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Add a new 'smp_init' hook to machine_desc so platforms can specify a
function to be used to setup smp ops instead of having a statically
defined value. The hook must return true when smp_ops are initialized.
If false the static mdesc->smp_ops will be used by default.
Add the definition of "bool" by including the linux/types.h file to
asm/mach/arch.h and make it self-contained.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Rename virt_smp_ops to psci_smp_ops and move them to arch/arm/kernel/psci_smp.c.
Remove mach-virt/platsmp.c, now unused.
Compile psci_smp if CONFIG_ARM_PSCI and CONFIG_SMP.
Add a cpu_die smp_op based on psci_ops.cpu_off.
Initialize PSCI before setting smp_ops in setup_arch.
If PSCI is available on the platform, prefer psci_smp_ops over the
platform smp_ops.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Will Deacon <will.deacon@arm.com>
CC: arnd@arndb.de
CC: marc.zyngier@arm.com
CC: linux@arm.linux.org.uk
CC: nico@linaro.org
CC: rob.herring@calxeda.com
When booting fewer cores than are physically present on a versatile
platform (e.g. when passing maxcpus=N on the command line), some
secondary cores may remain in the holding pen, which is marked __INIT.
Late in the boot process, the memory comprising the holding pen will be
released to the kernel for more general use, and may be overwritten with
arbitrary data, which can cause the held secondaries to start behaving
unpredictably. This can lead to all manner of odd behaviour from the
kernel.
Instead don't mark the section as __INIT. This means we can't reuse the
pen memory, but we won't get secondaries corrupting the rest of the
kernel.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Will Deacon has a better solution and his patch should
be coming in soon. In the mean time please consider for inclusion.
This is an in-between solution that prevents the EVENTEN bit in
the CNTKCTL register from being mask, resulting in events between
clusters being lost.
Bug: LP1188778
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
The CA9X4 CoreTile suffers from this errata and as a consequence has
reboot and shutdown crashes since the cpu hotplug changes introduced in
Linux 3.10. (Commit bca7a5a049 "ARM: cpu hotplug: remove majority of
cache flushing from platforms")
Signed-off-by: Jon Medhurst <tixy@linaro.org>
The patch removes a compiler warning when casting the ioaddr pointer to
(unsigned int) in the smc_probe() function of the smc91x.c driver. The
casting is now done to (unsigned long).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
During the free_pgtables() call all user and modules/pkmap entries are
removed. If a translation fault for the modules/pkmap area occurs before
we switched away from the current pgd, do_translation_fault() would copy
the init_mm pud into the user pud.
There is a small window between pud_clear() and pmd_free_tlb() in
free_pmd_range() where the pud entry was cleared but the TLB has not
been invalidated yet and the CPU may have cached the original (valid)
pud entry in the TLB. A scenario like below would get stuck in
continuous prefetch abort:
1. Current process exiting. The modules pmd entries not populated
2. exit_mmap() -> ... -> pmd_free_tlb()
3. pud_clear() for the 1GB pud containing user stack and modules (no TLB
invalidation yet)
4. Interrupt -> module interrupt routine
5. Level 2 (pmd) translation fault occurs when executing the module
interrupt routine. The CPU previously cached (TLB) the old valid pud
value for the modules area, so we don't get a level 1 translation
fault
6. do_translation fault() copies the pud_k into the pud
7. Linux returns to the faulty instruction. Goes back to 5
At point 7, since the CPU still has the old pud value, it goes back to
point 5 and never gets out of this loop. With this patch, the stale pud
TLB entry is invalidated after point 6 and the subsequent prefetch abort
doesn't occur.
Reported-by: Tony Thompson <Anthony.Thompson@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Configuration for the amba-clcd PL111 driver is added to the A9 CoreTile's DTS
file.
Configuration of the motherboard CLCD driver is disabled in the DTSI files to
prevent duplicate CLCD drivers being registered.
A generic set of CLCD panel descriptions has been split into its own DTSI file.
Currently, only XVGA and VGA monitors are described.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
The amba-clcd device can be configured to use either DMA or, when this
feature is not available, an ioremapped frambuffer in static ram.
In the case of the latter, we must take care not to pass ioremapped
addresses to dma_common_mmap, since this expects only addresses from
dma_mmap_coherent, which reside in the kernel linear mapping.
This patch reworks the fb initialisation code so that either DMA or IO
implementations of the mmap/remove functions are chosen as appropriate.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This patch hides the dma_(alloc|free)_writecombine() calls behind macros
to allow the amba-clcd.c to be used on architectures that do not provide
this DMA API. With this patch, the *_writecombine() API is only used on
ARM (AArch32).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This check was attempting to ensure only one clcd device in the
device-tree was probed, however the check fails in the valid case where
the device is a child of another device and the 'reg' value is a offset
from the start of that other device, not an absolute address. This
occurs on vexpress with the motherboard clcd being a child of iofga.
For now, we will just have to rely on there only being one display
device specified in device-tree.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
