According to E-EDID spec 1.3, table 3.9, a digital video sink with the
"DFP 1.x compliant TMDS" bit set is "signal compatible with VESA DFP 1.x
TMDS CRGB, 1 pixel / clock, up to 8 bits / color MSB aligned".
For such displays, the DFP spec 1.0, section 3.10 "EDID support" says:
"If the DFP monitor only supports EDID 1.X (1.1, 1.2, etc.)
without extensions, the host will make the following assumptions:
1. 24-bit MSB-aligned RGB TFT
2. DE polarity is active high
3. H and V syncs are active high
4. Established CRT timings will be used
5. Dithering will not be enabled on the host"
So if we don't know the bit depth of the display from additional
colorimetry info we should assume 8 bpc / 24 bpp by default.
This patch adds info->bpc = 8 assignement for that case.
Change-Id: Ie7603f8bf19eeeb1cd1988b6a245ead5d2e52763
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 210a021dab)
This is the content of
Case693349_the_spinlock_fix_patch_2_for_kernel_4.4.patch
from support_mali, with slight modifications for building
with rockchip_linux_defconfig,
in which CONFIG_SYNC is not set.
Change-Id: Icedff21f7941fd1aefceb6be4fda638378fe4ca8
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
The otg id voltage is provided from usb2 phy power. On some
rockchip platforms (e.g. rk3399), the usb2 phy power will be
turned off when enter pm suspend, this will trigger id fall
interrupt. But current code enable the ID interrupt consistently,
it may result in the mistake of ID changing operation even if
the state of ID pin is not changed. So disable ID irq when
suspend and enable when resume.
Change-Id: Icac35f13861fd639e4b422b31182a68add73836d
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
RK3228 uses the Synopsys DWC HDMI TX controller and the INNO HDMI PHY to
enabling the integration of a complete HDMI Transmmiter interface.
Change-Id: I90f997968fb2de4165a31216c8aee8213089eab5
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
INNO HDMI 2.0 TX PHY is compliant with HDMI 2.0 specification
and optimized up to 3.72Gbps per TMDS link High-Definition
applications with supporting 3D Display and up to 4Kx2K@60/50Hz
UHD resolution at 10-bit YCbCr 4:2:0 video input mode.
Change-Id: I1f8b2e5c656378188dca8e02df6d52bad2919da8
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
MEDIA_BUS_FMT_UYYVYY8_0_5X24 and MEDIA_BUS_FMT_UYYVYY10_0_5X30 are
bus_format of YUV420 data between Rockchip vop and Synopsys HDMI
TX Controller.
Change-Id: Id06e7cc7703e9b12e1a7f64cdbacc5e8a98b2b45
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
The plat_data->input_bus_format and plat_data->input_bus_encoding
are unsigned long and are always >=0, but the value 0 was still
considered as RGB888 for input_bus_format and default color space
for input_bus_encoding in the reworked code.
This patch changes the if statement check for a non-zero value to
either use the default input bus_format and/or bus_encoding for a zero
value and the provided bus_format and/or bus_encoding for a
non zero value.
Thanks to Dan Carpenter for his bug report at [1].
Tested on Amlogic P230 (with CSC enabled for YUV444 to RGB) and Rockchip
RK3288 ACT8846 EVB Board (no CSC involved, direct RGB passthrough).
[1] http://lkml.kernel.org/r/20170406052120.GA26578@mwanda
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: def23aa7e9 ("drm: bridge: dw-hdmi: Switch to V4L bus format and encodings")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
[narmstrong@baylibre.com: reworded commit message and added Fixes tag]
Link: http://patchwork.freedesktop.org/patch/msgid/1491471244-24989-1-git-send-email-narmstrong@baylibre.com
Change-Id: I1b6c08e3fe468c01fcd721fe4b4d6ec95c73528b
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit e20c29aa72)
Switch code to use the newly introduced V4L bus formats IDs instead of custom
defines. Also use the V4L encoding defines.
Some display pipelines can only provide non-RBG input pixels to the HDMI TX
Controller, this patch takes the pixel format from the plat_data if provided.
Change-Id: I2b70ed0f3cab8c6873bb407977738677375b24b0
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit def23aa7e9)
If the crtc pll status is not init, always cause mode_changed
at first dclk source generate, that would cause logo flush
fixup(10a90aa drm/rockchip: support setting specail pll for hdmi)
Change-Id: I0ee20fd098654ff89f268be82b50d2d5b605e9d5
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
gpio0_D is unavailable on rk3288 with current pinctrl driver.
Change-Id: I7d38ebd3b00ac0df31861406f758bdd9e57f9903
Signed-off-by: xcq <shawn.xu@rock-chips.com>
This reverts commit 1d9964a989.
Double confirmation, GPIO0_D0 ~ GPIO0_D7 pins are not connected to pad,
this is a wrong commit, revert this commit.
Change-Id: Iebec11ee47a68fe51ec90361fd412d05df832998
Signed-off-by: David Wu <david.wu@rock-chips.com>
First, write hdcp key by "ProvisioningTool" if you want to
enable hdcp function, or else will auth fail.
To check whether the hdcp is enable or not
#cat /sys/class/misc/hdmi_hdcp1x/enable
0:hdcp is disabled
1:hdcp is enabled, hdmi screen will be pink if it is failed;
2:hdcp is enabled, hdmi screen will be normal if it is failed;
Enable or disable hdcp function
#echo 0 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 1 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 2 > /sys/class/misc/hdmi_hdcp1x/enable
Get the status of hdcp
#cat /sys/class/misc/hdmi_hdcp1x/status
The result will be one of the follow list:
hdcp disable;
hdcp_auth_start
hdcp_auth_success;
hdcp_auth_fail;
unknown status.
Change-Id: Iac6c7d6a1196ce9cf2869d7916bbe6c8941ec13b
Signed-off-by: xuhuicong <xhc@rock-chips.com>
This patch exports sdio src clock for dts reference.
Change-Id: I3e83cce4da3d82af4b18df43ecd51c504d308c02
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
According to spec, TMDS driver should power up between PLL
power up and PLL lock.
There is an mistake of pdata en register, the real register
is reg2 bit0, not reg1 bit0.
Change-Id: I9d2b707cbcfd70b63f4a1a277a85f21b62643d2e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Actually vop hardware has no output height limit, so no
need limit display with max_output.height
Change-Id: Ide70cb28af9a23c1a12c068168b13aac37041b28
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
In order to get lower jitter clock for hdmi tmds, Hardware
design that: direct get tmds clock from vpll, bypass vop.
This design can make hdmi good works, but also limit hdmi's
clock source, the vop which hdmi use need also assign to vpll,
and use same clock rate, it's hardware limitation.
This patch add a mechanism to select dclk's parent pll, then
can allocate correct pll for hdmi.
Change-Id: I9e3b4b6d3756c409782df0605706be4203d69a32
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Suggested-by: Heiko Stuebner <heiko@sntech.de>
