Commit Graph

607072 Commits

Author SHA1 Message Date
Finley Xiao
0cb664eb76 clk: rockchip: px30: Remove clk_gpu_divnp5
Change-Id: I67f47f5fdd7873c22b1349e3aeb80b7157c7844c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-11 19:12:19 +08:00
Finley Xiao
f457f16cd2 clk: rockchip: px30: Fix clk_gmac_rmii_sel parent
Change-Id: Idf1bd416a3879048afd3763d4a6d056c34171bbb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-11 19:10:15 +08:00
Sandy Huang
ce0ec8d27b drm/rockchip: vop: alpha_pre_mul mode depend on user space
Change-Id: Iaada438902ddddbbd00890c53a58cc49af3c3d3e
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2018-02-11 19:08:48 +08:00
Sandy Huang
424a08f4cb drm/rockchip: px30 vop: delete win2
Change-Id: If36214c7f57c96d7a06e81db383300cff0669681
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2018-02-11 14:58:38 +08:00
Finley Xiao
aed92d3f61 clk: rockchip: px30: Fix clk_i2s0_rx parent
Change-Id: Ia523234cf5b210bbfe51cbf075943e7f44123ca9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-11 12:08:25 +08:00
Zheng Yang
5f1c036a65 drm/bridge: synopsys: dw-hdmi: fix kernel logo flash when output YCbCr422 mode
On rockchip platform, hdmi input format is YCbCr444 when output mode
is YCbCr422. Then the value of HDMI_TX_INVID0 on YCbCr422 is same as
the value of YCbCr444, both is 0x09/0x0b. This make enc_out_bus_format
stroed in struct hdmi_data is wrong, which is MEDIA_BUS_FMT_YUV8_1X24
or MEDIA_BUS_FMT_YUV10_1X30.

When android set enc_out_bus_format to YCbCr422, dw_hdmi_setup will be
called and logo will flash.

This patch use colorspace restored in HDMI_FC_AVICONF0 to distinguish them.

Change-Id: I6b913951b58fb47628617c11d6059bc1be4e370a
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
2018-02-11 10:21:53 +08:00
Zhong Yichong
80f0ef45db arm64: dts: rockchip: rk3326 evb: enable isp
Change-Id: I0a41db448bbb51afcaa4b538cf0aefac25e7c762
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-10 16:30:53 +08:00
Zhong Yichong
0bef3afae9 camera: rockchip: camsys_drv: disable cru reset of rk3326 isp now
Because it will cause CPU hangs on, so disable the reset temporarily.

Change-Id: I612be4b47145fd1ebf8d8e5d44270f26151768fa
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-10 16:29:56 +08:00
Zhong Yichong
f943a72c35 arm64: dts: rockchip: px30: modify isp mipiphy count from 0 to 1
Change-Id: I878c8b6ee15885662c215b52143cd73474dd8cbf
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-10 16:07:29 +08:00
Zhong Yichong
16bb8bd923 arm64: dts: rockchip: px30: modify the isp reg range
Change-Id: I3326908e0445c1230b73169b9d9b34a31658d0b2
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-10 16:07:19 +08:00
shengfei Xu
69441faf9e mfd: rk808: rk809 chip name register is same as rk817
Change-Id: I22f5735ab3272a53d2e97012f452c340f16b0bff
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
2018-02-10 14:58:46 +08:00
Rocky Hao
9b2724a451 thermal: rockchip: fix channal invertion issue for px30
Change-Id: Ifed5628c18cece0658754095e718da39ac703413
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-02-10 11:34:03 +08:00
Tao Huang
9b3f148373 ARM: rockchip_defconfig: enable CONFIG_MEMORY_STATE_TIME
f3d9c312b8 ("Implement memory_state_time, used by qcom,cpubw")

New driver memory_state_time tracks time spent in different DDR
frequency and bandwidth states.

Memory drivers such as qcom,cpubw can post updated state to the driver
after registering a callback. Processed by a workqueue

Bandwidth buckets are read in from device tree in the relevant qualcomm
section, can be defined in any quantity and spacing.

The data is exposed at /sys/kernel/memory_state_time, able to be read by
the Android framework.

Functionality is behind a config option CONFIG_MEMORY_STATE_TIME

Change-Id: Ic3b0b631efd697713360f193ede440cd9ad3bc29
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-10 10:34:38 +08:00
Tao Huang
319ff3657f arm64: rockchip_defconfig: enable CONFIG_MEMORY_STATE_TIME
f3d9c312b8 ("Implement memory_state_time, used by qcom,cpubw")

New driver memory_state_time tracks time spent in different DDR
frequency and bandwidth states.

Memory drivers such as qcom,cpubw can post updated state to the driver
after registering a callback. Processed by a workqueue

Bandwidth buckets are read in from device tree in the relevant qualcomm
section, can be defined in any quantity and spacing.

The data is exposed at /sys/kernel/memory_state_time, able to be read by
the Android framework.

Functionality is behind a config option CONFIG_MEMORY_STATE_TIME

Change-Id: I4391cc3ed42c9f332bce4a7809c6f120e2798dae
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-10 10:34:23 +08:00
Finley Xiao
884b0673a7 clk: rockchip: rk3288: Add TSP clock
Change-Id: I02185c5ab7a1072d271cd51161f6d4b05d327673
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-10 09:04:17 +08:00
Finley Xiao
a250f09aff clk: rockchip: rk3128: Add sclk_hsadc_tsp
Change-Id: I842869a7ea79730daa6616f1cf2a8f5db7165ceb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-10 09:04:17 +08:00
William Wu
33e05f0c21 CHROMIUM: phy: rockchip-typec: enable usb3 host after pipe ready
If we power off the SoC LOGIC rail in S3, we can find that the
Type-C PHY can't initialize correctly after system resume with
error log looked like this:
  phy phy-ff800000.phy.9: phy poweron failed --> -110
  dwc3 fe900000.dwc3: failed to initialize core
  dwc3: probe of fe900000.dwc3 failed with error -110

It's because that the field of usb3tousb2 in GRF_USB3PHY0/1_CON0
is reset to 1 after power off the SoC LOGIC, which means that the
pipe interface is blocked between Tpye-C PHY and usb3 controller.
And after system resume, the rockchip_usb3_phy_power_on() will call
the tcphy_cfg_usb3_to_usb2_only() to clear the usb3tousb2 bit and
enable the usb3 host again. If we clear the usb3tousb2 bit before
pipe ready, it may cause waiting for pipe ready timeout.

Note that the RK3399 TRM suggests that we should keep the whole usb3
controller in reset for the duration of the Type-C PHY initialization.
However, it's hard to assert the reset in the current framework of
reset. And according to the TRM, it doesn't require that we should
clear the usb3tousb2 bit before pipe ready. So let's enable the usb3
host after pipe ready to avoid the Type-C PHY initialization failure.

BUG=b:62644399, chromium:783464
TEST=run suspend_stess_test on Scarlet, usb device can work after resume

Change-Id: Ie597cbe35568c390460aa2fdbad0e66c6104c8d2
Reviewed-on: https://chromium-review.googlesource.com/896908
Commit-Ready: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-02-10 09:03:29 +08:00
William Wu
fd186f221b CHROMIUM: usb: dwc3: rockchip: reset host controller at resume
If we power off the SoC LOGIC rail in S3, it seems that the host
controller comes back in an undefined state, such that the Type C PHY
can't initialize correctly. We need to toggle the USB3-OTG reset before
trying to initialize the PHY, or else it often times out.

Note that the TRM suggests we should be asserting this reset for the
duration of the PHY initialization, but we're still skeptical about
that, and we haven't yet found a case where this seems to have mattered.
Besides, this approach is much easier.

The dwc3 core is going to reinitialize the controller at suspend/resume
anyway (including a "soft reset"), so it should be safe to do this,
regardless of whether the system actually powered off the USB logic.

For hygiene's sake, it's good to wait some small bit of time in between
asserting/de-asserting this reset. Might as well apply this to both
instances of this reset.

BUG=b:62644399
TEST=suspend/resume scarlet with LOGIC disabled in S3; USB comes back OK
     also test suspend/resume on kevin for USB regressions

Change-Id: I5b5354d0fb9c7ed9d2c9044ddfbb5f7709884fb7
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/877404
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2018-02-10 09:03:29 +08:00
David Wu
f8c5fa1e6b arm64: dts: rockchip: increase the i2c1 scl frequecny to 400k for rk3326-evb-lp3-v10
Base on the rise time of scl test, the scl frequecny could be
increased to 400k.

Change-Id: I17f858b28ed11992411c52e5f83424b0187d097c
Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-02-10 09:02:25 +08:00
David Wu
99079676c2 arm64: dts: rockchip: increase the i2c0 scl frequecny to 400k for rk3326-evb-lp3-v10
Base on the rise time of scl test, the scl frequecny could be
increased to 400k.

Change-Id: I9af57e13a97f0866ec4f0dd295f9bcf4cbeee304
Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-02-10 09:02:07 +08:00
Huibin Hong
68b095de9e spi: rockchip: add compatible rockchip,px30-spi for px30
Change-Id: Ibe406477b3912b482d07e5c0e7f8e2e99a51bd4a
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09 18:57:11 +08:00
Huibin Hong
02dcfc3420 arm64: dts: rockchip: add uart aliases, modify uart1 clk for px30
Change-Id: Ia1accabbb76c1f1e4deb11aae055bec328ec5a61
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09 17:57:09 +08:00
Huibin Hong
d51654309d spi: rockchip: test: remove unused code
Change-Id: I7b44f7c3a8e32eaf2c550d915c45a3394816c925
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09 17:56:22 +08:00
Tao Huang
4b4a117433 ARM: rockchip_defconfig: enable CONFIG_AIO
4ed084e489fd ("Move CONFIG_AIO to android-base.")

CONFIG_AIO has legitimate use for the functionfs
driver, which is used with adb and mtp. It is now
required to be enabled for better performance
with those services.

Change-Id: I52d05c734a25b35e012666b010b2ee5426915094
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 17:54:35 +08:00
Tao Huang
6f04df2fa9 arm64: rockchip_defconfig: enable CONFIG_AIO
4ed084e489fd ("Move CONFIG_AIO to android-base.")

CONFIG_AIO has legitimate use for the functionfs
driver, which is used with adb and mtp. It is now
required to be enabled for better performance
with those services.

Change-Id: I631fac8e56ea16711f0cc05297140dc59c9fb581
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 17:54:25 +08:00
Huibin Hong
6716ded459 arm64: dts: rockchip: add spi1 cs1 for px30
Change-Id: I933b76ed4b312a713e390c130ef6b5c090e3779c
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09 17:49:42 +08:00
Tao Huang
e868d4ecb9 ARM: rockchip_defconfig: remove CONFIG_PM_AUTOSLEEP
6e30a9a158bd ("remove CONFIG_PM_AUTOSLEEP from android-base.cfg")

Autosleep is no longer used by Android.

Change-Id: Ia024dbb6343abd8e1016febc08251dc5dc7badc1
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 17:33:47 +08:00
Tao Huang
3c4e6c9040 arm64: rockchip_defconfig: remove CONFIG_PM_AUTOSLEEP
6e30a9a158bd ("remove CONFIG_PM_AUTOSLEEP from android-base.cfg")

Autosleep is no longer used by Android.

Change-Id: I7ff5c40a8cdfbe9e67019bc859eb940fae2b6c4f
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 17:33:40 +08:00
Algea Cao
0b86943d0e mfd: rk1000: Support rk1000 uboot logo
Reading rk1000's register to see whether uboot logo was on.

Change-Id: Iee6d15213f16ccd59136a5cf4f4017f5cd40ab62
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-02-09 16:44:58 +08:00
Algea Cao
4262e671f9 arm64: dts: rk3368-r88: support rk3368 drm cvbs uboot logo
Removing ports so that uboot display subsystem can get
rk1000 as panel.

Change-Id: If12c30bb7d1bd382ed969534687234aa79b8dd04
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-02-09 16:44:41 +08:00
Algea Cao
bcc83cb2ff drm/bridge: Support rk1000 kernel logo
Setting connector port to support kernel logo

Change-Id: I594eec0a924ecf1c47c82d61c471dd21c2af1830
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-02-09 16:44:17 +08:00
shengfei Xu
569bb500f8 arm64: dts: rockchip: rk3326: use extcon specifier for the charger
Change-Id: Ie84c6be541c6489ca93cef38f5ad3741851fdb59
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
2018-02-09 16:40:07 +08:00
Sandy Huang
d06bd5047d drm/rockchip: vop: default set to premultiplied alpha mode
Change-Id: I006d2d7bda2413d3796a14c23a34fe2beea878a8
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2018-02-09 16:38:20 +08:00
Tao Huang
393a65de77 ARM: rockchip_defconfig: remove USB_OTG_WAKELOCK
cc756e682c ("ANDROID: android-base.cfg: remove USB_OTG_WAKELOCK")

CONFIG_USB_OTG_WAKELOCK is currently somewhat outdated
and as such is not applicable to all Android devices. Until
it is brought up to date, remove it from the base Android
kernel configuration.

Change-Id: I4d6a2ba78ddc9210bc949ee2ecc5182a4814715d
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 16:38:07 +08:00
Tao Huang
4db3204bdb arm64: rockchip_defconfig: remove USB_OTG_WAKELOCK
cc756e682c ("ANDROID: android-base.cfg: remove USB_OTG_WAKELOCK")

CONFIG_USB_OTG_WAKELOCK is currently somewhat outdated
and as such is not applicable to all Android devices. Until
it is brought up to date, remove it from the base Android
kernel configuration.

Change-Id: Id112f1e692fce021b8ab5437ae7811c216c8d272
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 16:37:51 +08:00
Tao Huang
7f9eafd047 ARM: rockchip_defconfig: remove NETFILTER_XT_MATCH_QUOTA2_LOG
bc86c1de1d ("ANDROID: android-base.cfg: remove NETFILTER_XT_MATCH_QUOTA2_LOG")

There are currently a couple different implementations for this
functionality. Until things are unified, remove the requirement
for this kernel config.

Change-Id: Ia3f515452871118dab4b8688ff9fd16e87beb9b6
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 16:37:31 +08:00
Tao Huang
ce71feccf9 arm64: rockchip_defconfig: remove NETFILTER_XT_MATCH_QUOTA2_LOG
bc86c1de1d ("ANDROID: android-base.cfg: remove NETFILTER_XT_MATCH_QUOTA2_LOG")

There are currently a couple different implementations for this
functionality. Until things are unified, remove the requirement
for this kernel config.

Change-Id: Ibbe93ae71d4b7512be397e689abc36ba51011b30
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 16:37:22 +08:00
David Wu
880bdfc097 arm64: dts: rockchip: Change the pinctrl name sdmmc0 to sdmmc for px30
Change-Id: I57a4d732337fcf4356234e58658dd82655e53751
Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-02-09 16:12:07 +08:00
Zhou weixin
f4d7a8591d arm64: dts: rockchip: px30: Add sdmmc iomux
Change-Id: I3debec6ca7010d2e15f1302d3403852a951da768
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
2018-02-09 16:11:42 +08:00
David Wu
7c4d90fc8a arm64: dts: rockchip: Remove unused sdmmc1 pinctrl for px30
1. remove sdmmc1 pinctrl
2. move sdio pinctrl to sdmmc together

Change-Id: Ibcde69298cfdfdd99228de941082cde6be6dfa6b
Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-02-09 16:11:36 +08:00
shengfei Xu
75b2bdbcf3 mfd: rk808: fix the shutdown function for rk817
Change-Id: Ieb980e9d2c779821d90061e79cebd302554176fc
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
2018-02-09 16:10:50 +08:00
Tao Huang
b14ec5d805 ARM: rockchip_defconfig: remove CONFIG_CGROUP_DEBUG
97841e574a ("ANDROID: android-base.cfg: remove CONFIG_CGROUP_DEBUG")

This config option is not required by Android.

Change-Id: I2c57f98f94465d56aac60fe12b9b4d0a42d42242
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 15:46:47 +08:00
Tao Huang
d0524a0531 arm64: rockchip_defconfig: remove CONFIG_CGROUP_DEBUG
97841e574a ("ANDROID: android-base.cfg: remove CONFIG_CGROUP_DEBUG")

This config option is not required by Android.

Change-Id: Ica7ed956e2340d5fd8756a400d13725799857423
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 15:25:06 +08:00
shengfei Xu
edd344986f power: rk817: fix the error when plug in OTG
[   36.485506] [<ffffff80080b97c0>] __queue_delayed_work+0x6c/0x148
[   36.485523] [<ffffff80080b98ec>] queue_delayed_work_on+0x50/0x6c
[   36.485543] [<ffffff80087315c4>] rk817_charge_host_evt_notifier+0x20/0x2c
[   36.485561] [<ffffff80080c0c54>] notifier_call_chain+0x48/0x80
[   36.485576] [<ffffff80080c0cdc>] raw_notifier_call_chain+0x14/0x1c
[   36.485596] [<ffffff8008855b10>] extcon_sync+0x74/0x1c4
[   36.485615] [<ffffff80083c3118>] rockchip_usb2phy_id_irq+0x270/0x2b8
[   36.485633] [<ffffff80080f84ac>] irq_thread_fn+0x28/0x68
[   36.485648] [<ffffff80080f8070>] irq_thread+0x100/0x1d8
[   36.485662] [<ffffff80080bfc80>] kthread+0xe8/0xf0
[   36.485678] [<ffffff80080832a0>] ret_from_fork+0x10/0x30

Change-Id: Ib1a50dbf2210e43efb056835e4fef1caae2ca059
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
2018-02-09 15:24:25 +08:00
Liang Chen
57123b5e03 arm: dts: modify dmc frequency of normal to 600M for rk322x
Change-Id: Idbff23336040ac33c6906cc350483f0877e216e4
Signed-off-by: Liang Chen <cl@rock-chips.com>
2018-02-09 15:03:20 +08:00
Shawn Lin
3cd33bec92 arm64: dts: rockchip: correct ep-gpios for rk3399 sapphire PCIe slot
Change-Id: I349d7f9267e50d90afb12902ee4ced98f8e4cfa5
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2018-02-09 14:19:08 +08:00
Algea Cao
762aa32d74 ARM: dts: rk3288-android: Add hdmi route
Change-Id: I0c0848abac414b1c03afc564a2375e12ec9ab422
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-02-09 11:32:08 +08:00
Binyuan Lan
f29923d120 arm64: dts: rockchip: add headset detect for rk3326
Change-Id: Ia816a8f8fdcdd2265841965a59654e3b5f13cc06
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
2018-02-09 11:28:13 +08:00
Zorro Liu
caf5f86288 Revert "drivers: input: sensors: reset sensor rate"
This reverts commit 3726b810fe.

Change-Id: I23692bb090f5a1c946b57071366d4611bc3d7189
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
2018-02-09 11:24:29 +08:00
Zorro Liu
a5e68c507a drivers: input: sensors: add gsensor stk8baxx
Change-Id: I983df89f746e42221009e9123116900041b9a06a
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
2018-02-09 11:24:13 +08:00