The registers relative with fuel gauge must be volatile.
Change-Id: I8e942e8f15f66dabf24ede48b81857947575fa23
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Because the default frequency is 300M will cause green horizontal
stripes when in 4K resolution zoom mode:
Change-Id: Ia571e8eb32ba62ee3e3857e2a1ee3187a14e408f
Signed-off-by: Alex Wang <alex.wang@rock-chips.com>
From u-boot 5e817a0ea427 ("tools: rockchip: resource_tool: add sha1 for file entry").
Merge all C files to one resource_tool.c
Change-Id: If63ba77d1f5a3660bd6ef87769bb456fa086ae71
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
On an eDP connection, the eDP sink must operate only in Enhanced Framing Mode.
The Source must send only Enhanced Framing on the main link, and must only
write a '0' to DPCD 00101h: LANE_COUNT_SET Bit 7: ENHANCED_FRAME_EN bit.
Independent of method used, DP1.2-compliant eDP Receivers shall indicate any
eDP protocol differentiation method they support through the Receiver
Capability Field of DPCD (DPCD:0000Dh).
Change-Id: Ia57f3242c16e2ace0c13076992c2c14eda9e7ca7
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
DP firmware uses fixed phy config values to do training, but some
boards need to adjust these values to fit for their unique hardware
design. So get phy config values from dts and use software link training
instead of relying on firmware, if software training fail, keep firmware
training as a fallback if sw training fails.
Change-Id: I075bff6aa153a5e18b6a5ddec2645131f1411913
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Change-Id: I195727b2a81130606e66ffc4471df74e5782a7fa
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
the new drm driver remove idr alloc for DRM_MINOR_CONTROL, so we use
DRM_MINOR_PRIMARY to get drm device for dmc.
Change-Id: I5ac524cb98bfc4431305e341b5c659aa865bb670
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The power of fusb302 is controlled by GPIO1_C2 which should be set as
ACTIVE_HIGH and it was set incorrectly in this dtsi file leading to cannot
send notifie.
Change-Id: Ibc045d266e5bc9718343e07acda8488b0d747aba
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
In kernel 4.4, we use the extcon notification function in dwc3-rockchip.c
to perform the drd mode switch. Kernel 4.19 implements the same
functionality in drd.c and writes the extcon notification function in
core.c. So we need to move extcon to the subnode of dwc3.
Besides, I deleted some useless code which is wrongly copied.
Change-Id: I1096e64d5a29f01c94a10027b846676033c7985d
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
In kernel 4.4, we use the pm runtime mechanism in dwc3-rockchip.c to
implement usb power management. In kernel 4.19, dwc3-rockchip.c is not
required for drd mode switching, and the extcon notification function is
written in core.c. So we use the runtime in core.c to implement power
management.
Change-Id: I483ce061a5b7b5a348e679d39c559a4ca29a40b8
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
The ROM code for Rockchip platform never support detecting
SD 3.0 mode, so if the SD card contains system image running
into SD 3.0 mode in kernel, it will fails to reboot.
The problem is SD 3.0 mode is using 1.8V signal and could only
be switched back into 2.0 mode by power cycle. If the customed
board could not switch off its power rail, the ROM code can't
soft reset the SD.
Add mmc_sd_shutdown to workaround this special case and don't
bother normal SD cards used as external disk by checking the
RESTRICT_CARD_TYPE_MMC flag.
Conflicts:
drivers/mmc/core/sd.c
Change-Id: I4c3d3111c0bce0ad3cd4f0c6592ff595d7015afe
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
drivers/soc/rockchip/rockchip_system_monitor.c:579:2: warning:
Attempt to free released memory
Change-Id: I7bba708b6457fed0553a56ec7f943311a490fbb8
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Fix display abnormal caused by DDR frequency conversion.
Change-Id: Iaa3bf6177d42f8ac5f9078b58a138f48d5c1d874
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
1. use 856MHz in order to enable write dq odt, because Samsung lp4 write
dq odt can not enable when frequency under 800MHz
2. 416MHz and 856MHz is the frequency avoid disturb wifi 2.4GHz
Change-Id: Icbcd2a78dbcbfe33bc3e5b0e296913dea4b28480
Signed-off-by: CanYang He <hcy@rock-chips.com>
some frequency not fix VDD_CENTER to 0.9V, although these frequency not
enable, to prevent these frequency being enable, fix all VDD_CENTER to
0.9V
Change-Id: I711bf091962f1ca1508b2611bfcaf26e37e451fd
Signed-off-by: CanYang He <hcy@rock-chips.com>
There is crypto hardware in RK3128 but NOT in RK3126C.
Change-Id: Ie5ab4e2565a34b7ea963f21793b46cafdf8a2c7f
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
According to xHCI spec v1.1 section 6.4.5 TRB Completion Codes,
the standard XHCI controller provide a TRB Completion Status
'USB Transaction Error' to asserted in the case where the host
did not receive a valid response from the device, it's useful
to handle pending URBs on the endpoint when the USB device is
plugged out.
Unfortunately, some SOCs USB 3.0 modules lose the ability to
assert the 'USB Transaction Error' status when USB 3.0 device
disconnect. This may cause the pending URBs unhandled, even
lead to USB class driver stalled in waiting for URBs complete.
This patch flush pending URBs in usb_disable_device() when
USB 3.0 device disconnect, it will call xhci_urb_dequeue()
-> xhci_queue_stop_endpoint() to cancel pending URBs and
giveback URB status immediately.
Change-Id: If8acac59bc1f2c10a41ee390ccbeb84b2e7743c1
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Some special SoCs (e.g. rk322xh) USB3 PHY have problem to detect
disconnection, they lose the ability to detect an absence of Rx
termination specified in USB3 spec Table 6-21, fortunately, the
USB3 PHY can detect port link state change when USB3 device is
unplugged, so we can do soft disconnect according to the PLC.
Change-Id: I2cbd62fddc8a1f9c5a264d705db43fb0cf3e035c
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Some xHCI controllers (e.g. Rockchip rk3328 SoC) integrated
in DWC3 IP, don't support USB 3.0 autosuspend well, so we
need to disable USB 3.0 HUB autosuspend function with a quirk.
Change-Id: I33d4d2ec86102653bfb043eed12bfb6b5b426823
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds a new property "snps,dis-u3-autosuspend-quirk" for
xHCI integrated in DWC3 IP to disable USB 3.0 root HUB autosuspend.
Change-Id: Ibaf2b8d0e0472b052d3ab46010b7477274f4bb78
Signed-off-by: William Wu <william.wu@rock-chips.com>
Some USB controllers (such as rk3328 SoC DWC3 controller with INNO
USB 3.0 PHY) don't support autosuspend well, when receive remote
wakeup signal from autosuspend, the Port Link State training failed,
the correct PLC is Resume->Recovery->U0, but when the issue happens,
the wrong PLC is Resume->Recovery->Inactive, cause resuming SS port
fail. This issue always occurs when connect with external USB 3.0 HUB.
This patch adds a quirk to disable xHC USB 3.0 root HUB autosuspend
function.
Change-Id: I6afade864235a7669f415d933b7b4983c0d46289
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds a new "usb3-dis-autosuspend" property for some
Rockchip platforms which don't support autosuspend well.
Change-Id: I4d035415456405d47b85b3619fb47eb617fd2303
Signed-off-by: William Wu <william.wu@rock-chips.com>
Some USB host controller seems to have problems with
autosuspend. For example, Rockchip rk3328 SoC USB 3.0
wouldn't handle remote wakeup correctly with external
hub after entered autosuspend, caused to resume SS
port fail.
This patch introduces a new quirk flag for hub that
should remain disabled for autosuspend.
Change-Id: I6d14222b2c5025583fea811a6afd6abd22f41cb9
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch tries to get the USB3 PHY using, and associates
the XHCI shared_hcd device with it.
With this patch, the USB HUB core driver can do USB PHY
operations base on USB PHY framework, e.g. call usb_phy_
notify_connect() or usb_phy_notify_disconnect() to notify
USB PHY driver to do soft connect or soft disconnect.
Change-Id: I3b51181b840a68ae477b764013446f49dbf7ca70
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch doesn't fix any issue but make the code more concise.
Change-Id: I56d9d0e5f13579d2087edc41ca83bdb00e1ebb3f
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch fixes somme compile errors base on new
xHCI port structure.
Change-Id: Ic9c90b6523e0bebcaeaf1fead23bd0474e85d96a
Signed-off-by: William Wu <william.wu@rock-chips.com>
Fix sparse warning:
drivers/phy/rockchip/phy-rockchip-typec.c:403:16: warning: symbol 'usb3_pll_cfg' was not declared. Should it be static?
drivers/phy/rockchip/phy-rockchip-typec.c:420:16: warning: symbol 'dp_pll_cfg' was not declared. Should it be static?
Change-Id: I5c814f7d62a806deb53331e729008dd35bdfd790
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit f7f6ed925d)
CONFIG_AUDITSYSCALL are enabled by default. This causes the
audit of all system call which impacts performance.
Disable these unused configs to improve performance.
Change-Id: I6487ab4034bd48a183107044be9c127b4bd435b6
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
CONFIG_AUDITSYSCALL are enabled by default. This causes the
audit of all system call which impacts performance.
Disable these unused configs to improve performance.
Change-Id: I7a147989dcaaf5c22d3d6d17e24f16ea38384d85
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
