We observed the failure of initializing card after resume
accidentally. It's hard to reproduce but we did get report from
the suspend/resume test of our RK3399 mp test farm . Unfortunately,
we still fail to figure out what was going wrong at that time.
Also we can't achieve it by retrying the host->f_init without falling
back it. But this patch will solve the problem as we could add some log
there and see that we resume the mmc card successfully after falling
back the host->f_init. There is no obvious side effect found, so it seems
this patch will improve the stability.
[ 93.405085] mmc1: unexpected status 0x800900 after switch
[ 93.408474] mmc1: switch to bus width 1 failed
[ 93.408482] mmc1: mmc_select_hs200 failed, error -110
[ 93.408492] mmc1: error -110 during resume (card was removed?)
[ 93.408705] PM: resume of devices complete after 213.453 msecs
Change-Id: I5b24cb84a223394392450a1f10d8bbacb9e1006e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
We will reuse it outside the core.c file, so let's
move it to the header file.
Change-Id: Ibc40268d104d503603d59911d71157fcee0e5196
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
wait_event_interruptible_timeout() will return early if the blocked
process receives a signal, causing the driver to abort the tuning
procedure and possibly leaving the controller in a bad state. Since the
tuning command is expected to complete quickly (<50ms) and we've set a
timeout, use wait_event_timeout() instead.
Change-Id: Ibd1c5e8076c5fde4b4e9c4ebb0a2733c8d2d4eda
Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Tested-by: Robert Foss <robert.foss@collabora.com>
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Let's keep genpd for sdhci alive while entering deep
sleep which gte me out of yapping around.
Change-Id: I0da20b417621d277745bafd53d1ee461aae72e11
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The DesignWare USB3 integrated in rockchip SoCs is a configurable
IP Core which can be instantiated as Dual-Role Device (DRD), Host
Only (XHCI) and Peripheral Only configurations. For rk3399, it has
two DWC3 controllers, we set DRD for DWC3_0 and Host only for DWC3_1
by default.
Change-Id: Ia0063e04e48770d8d0ec7ec86cb621c5e9979fb9
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
For now, we have enabled Type-C phy, so we can add
usb3 phy which integrated in Type-C phy for rk3399
dwc3, and support super speed.
Change-Id: I3da984e4f35b35d46e0b84755bcc23deaf97d18f
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
We can assert the reset to keep the whole USB3 Controller
in resetting to hold pipe power state in P2 before
initializing Type-C PHY.
Change-Id: Ibb5716bac645ae01ee27fd019a3dfcbd3c0ffd84
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
We enable PM runtime auto suspend on rockchip platforms (e.g. rk3399),
it allows DWC3 controller to enter runtime suspend if usb cable detached.
So we don't need to do anything in dwc3_suspend() and dwc3_resume()
which duplicated the same operations as dwc3_runtime_suspend() and
dwc3_runtime_resume().
And if DWC3 controller works on HOST mode, we can't do runtime resume
DWC3 gadget.
Change-Id: I63e734f51b05274251d8a88a664eee768568eb7b
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The otg_sm_work is a OTG state machine delay work. It will hold
a wake lock if SDP cable or CDP cable is attached, and release
the wake lock if cable dettached. If usb controller(e.g. DWC3)
call phy exit When USB cable is dettached and cancel otg_sm_work,
it will cause the usb phy keeping hold of wake lock.
Change-Id: Ie6a89e481b8d4999a996083709bacc5be901805a
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Add rockchip specific glue layer to support USB3 Peripheral mode
and Host mode on rockchip platforms (e.g. rk3399).
The DesignWare USB3 integrated in rockchip SoCs is a configurable
IP Core which can be instantiated as Dual-Role Device (DRD), Host
Only (XHCI) and Peripheral Only configurations.
We use extcon notifier to manage usb cable detection and mode switch.
Enable DWC3 PM runtime auto suspend to allow core enter runtime_suspend
if USB cable is dettached. For host mode, it requires to keep whole
DWC3 controller in reset state to hold pipe power state in P2 before
initializing PHY. And it need to reconfigure USB PHY interface of DWC3
core after deassert DWC3 controller reset.
The current driver supports Host only and Peripheral Only well, for
now, we will add support for OTG after we have it all stabilized.
Change-Id: I821dd19eedec73e6517f0cca184f939a9f313904
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
commit b1c127ae99 ("usb: host: xhci: plat: make use of new methods in
xhci_plat_priv") sets xhci->quirks before calling xhci_gen_setup(), which
will overwrite them.
Don't overwite the quirks, just add the new ones
Fixes: b1c127ae99 ("usb: host: xhci: plat: make use of new methods in xhci_plat_priv")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Change-Id: I7751ccaa1f3c8000ad0d47f9fba84084b2db96da
Cc: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 757de492f2)
We have merged dwc3 driver from upstream, and some properties
need to be modified according to upstream coding style.
Change-Id: I4f8c4b23a941932a08eb29a0282dfb0903193c8a
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
On some xHCI controllers (e.g. Rockchip SoCs), which are
integrated in DWC3 IP, need an extraordinary delay to wait
for xHCI enter the Halted state(i.e. HCH in the USBSTS
register is '1'), especially if DWC3 is in DRD mode.
Change-Id: I67c84d4768df95f7616d6716a77cf743e4334122
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Change-Id: I8b45a43a1a2c0399188d601c794015b4305c4795
Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Change-Id: I84ce14c328aa27c5000cf76c44cbdc1ea7a926b9
Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Support to configure the UTMI+ PHY with an 8- or 16-bit
interface via DT. The UTMI+ PHY interface is a hardware
capability, and it's platform dependent. Normally, the
PHYIF can be configured during coreconsultant.
But for some specific USB cores(e.g. rk3399 SoC DWC3),
the default PHYIF configuration value is false, so we
need to reconfigure it by software.
Change-Id: I5c5a44dcd9ef4c3b8f2b722cd066819a2983fcfc
Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Change-Id: I1b93715501f54231fc4dccebba2163d3484b2be6
Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Since commit (f6972eb FROMLIST: drm/panel: add of display
timing support), when panel has no device-tree timing, would always
get noise message:
[ 8.742157] /lvds_panel: could not find display-timings node
[ 8.747878] /lvds_panel: no timings specified
Change-Id: I9104b3017faa837807a09c21d0f948e499827ad9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
If detect a SDP charger type, we retry twice more to avoid
DCP falsely identified as SDP due to hardware signal error.
Change-Id: I1bf7bd076cd7767938f6944f1156daa7e64870e4
Signed-off-by: Feng Mingli <fml@rock-chips.com>
We're making all reset line users specify whether their lines are
shared with other IP or they operate them exclusively. In this case
the line is exclusively used only by this IP, so use the *_exclusive()
API accordingly.
Change-Id: I94d96af42ac63cd0c6445930f0458d36ec92f0e4
Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 5baaf3b9ef)
On the STiH410 B2120 development board the MiPHY28lp shares its reset
line with the Synopsys DWC3 SuperSpeed (SS) USB 3.0 Dual-Role-Device
(DRD). New functionality in the reset subsystems forces consumers to
be explicit when requesting shared/exclusive reset lines.
Change-Id: Id9ff5e3beadada3aeb5dc8a6085d9bd86255f45c
Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 002f17bc54)
It had changed to be suspend event for BIT6 in DEVT register from
version 2.30a and above. Thus this patch introduces one suspend
event handler to handle the suspend event.
Change-Id: I62751ee39a2ff13c1359350a8f6c43c14aa4ea12
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 72704f876f)
Implementations might use different IRQs for
host, gadget so use named interrupt resources
to allow device tree to specify the interrupts.
Following are the interrupt names
Peripheral Interrupt - peripheral
HOST Interrupt - host
Maintain backward compatibility for a single named
interrupt ("dwc3_usb3") for all interrupts as well as
unnamed interrupt at index 0 for all interrupts.
As platform_get_irq() variants are used, tackle
the -EPROBE_DEFER case as well.
Change-Id: Idb47d85ceee3353a219e4a9793942c7e92a6a6eb
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
(cherry picked from commit 9522def400)
Conflicts:
drivers/usb/dwc3/core.c
It will be crash to stop gadget when the dwc3 device had been into suspend
state, thus we need to check if the dwc3 device had been into suspend state
when UDC try to stop gadget.
Change-Id: I1a49d4c52131ef4b4357d4a12b5da55e8127d750
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit da1410be21)
Because of recent changes to transfer handling on
DWC3, we will not get XferComplete unless we
completely fill up our TRB ring. This means that we
might get a Reset or Disconnect without getting a
XferComplete first.
In order to correctly release our allocated Transfer
Resource, we must issue ENDTRANSFER command whenever
dep->resource_index is valid.
Change-Id: I6f78a239e26d754c2472f06789f820d42261d31d
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 0e146028ee)
If there is a failure after pm_runtime_enable/get_sync()
we need to call pm_runtime_disable/put_sync().
Otherwise it will lead to an unbalanced pm_runtime_enable() on the
subsequent probe if the earlier probe bailed out due to -EPROBE_DEFER.
pm_runtime_get_sync() can fail as well so deal with that case too.
Change-Id: Ia8af31867e996eeee4b0a18e34303280b661a86c
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 328082376a)
it's clear now that when is_on=true, we must loop
until DWC3_DSTS_DEVCTRLHLT clears; while when
is_on=false we must loop until DWC3_DSTS_DEVCTRLHLT
gets set.
Instead of adding actual if() statements, we can
rely on XOR operation to evaluate to true only when
the above conditions apply. Then, we can move the
break condition back to the while() statement
together with our timeout check and the resulting
code is very compact and simpler to read.
Change-Id: Id540c7422cd1d7e00120c26353d99e2e9888ea26
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit b6d4e16e83)
instead of looping forever and forcing a return if
timeout reaches zero, we can just use timeout and
loop's break condition directly.
Change-Id: Ibfbe125651d117cab717c5b0b73ef534ced79a67
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit f2df679b6c)
testing shows that udelay() is unnecessary as
controller reaches Halted state almost
instantenously as can be seen by our timeout
variable never actually decrementing.
Change-Id: I39aa43a4d26c4e5bf7c2c49569bb5ab0c662e718
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit d807bdd028)
We shouldn't change a host-only dwc3 to gadget-only
if driver is built as gadget-only. Fix that up here.
Change-Id: I7ff835a565e1d4d06e142f3fa9990ce96e85556e
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 5f82279a0c)
It's know that Intel's SoCs' dwc3 integration is
peripheral-only since Intel implements its own
portmux for role-swapping. In order to prevent dwc3
from ever registering and XHCI platform_device,
let's just set dr-mode to peripheral-only on Intel
SoCs.
Change-Id: Ic7a57ae89a4ea2a2f04a1aff581d728add15a034
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit e6fe66fe08)
'modify' is what the current action is called. Let's
rename it so it matches databook. While at that,
also make sure to add support 'init' action too.
Change-Id: I9fb3b445a7f8dd6acb369407eddf6d7d0994543d
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 21e64bf20d)
If we don't, we will overwrite valid TRBs.
Change-Id: I8076fa857b9ae016617d58836de3d9dcf5be9e4c
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit d6dc2e76a8)
Now we can try to issue Update Transfer every time
gadget driver queues a new request. This will make
sure we keep controller's queue busy for as long as
possible.
Change-Id: Id0418f2b4930e442d3bae7be87270100c0b347f5
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit ba62c09d5c)
We don't need this IRQ anymore for interrupt or bulk
endpoints.
Change-Id: I223ef88f807d7265a00d8d7be480320722d7ef88
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 13fa2e69b1)
Let's only set LST bit when we run out of space in
our TRB ring. For all other cases, we keep LST bit
unset which will prevent constant allocation and
deallocation of endpoint transfer resources.
Change-Id: Ia846ea0e3540c151d04488f239eb0f847c85b1fd
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 55a0237f8f)
