As pointed out by Stephen Rothwell, commit e52117638b ("ARM: dts:
omap3: Add DT entries for OMAP 3 ISP") conflicts with b8845074cf
("ARM: dts: omap3: add minimal l4 bus layout with control module support")
in non-obvious ways, causing a build failure when both patches
are present.
This merges the two branches that introduce the respective changes
into the next/late branch to resolve the way that Stephen suggested,
as confirmed by Tony.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.org/lkml/2015/4/6/436
Acked-by: Tony Lindgren <tony@atomide.com>
Pull "The i.MX device tree updates for 4.1" from Shawn Guo:
- Convert GPC controller to use stacked interrupt domains
- Add power domain descriptions for i.MX6 platforms
- Improve i.MX25 pin function defines
- Disable PWM devices in <soc>.dtsi by default and enable it at board
level dts where the device is actually available.
- Define labels for SNVS RTC device to ease the board description,
where an external RTC is available.
- Add dr_mode host setting to all i.MX host-only USB instances
- Support Miscellaneous System Control Module (MSCM) for VF610
- Add initial i.MX6SL WaRP Board support
- Add i.MX6SX SDB revision B board support
- A bunch of imx28-apf28dev board updates, including gpio polarity
correction and CAN, AUART device support.
- SolidRun iMX6 platform updates: dual-license of GPLv2/X11, PWM
setup, PCF8523 RTC, GPIO key and SGTL5000 audio support.
- A number of random device additions for boards: SPI and CAN for
vf-colibri, MAX7310 GPIO expander for imx6qdl-sabreauto and LCD
support for imx25-pdk.
Note: Branch imx/cleanup was merged as the base to solve conflict on
imx25 iomux header. Branch imx/soc was merged as the base to solve
conflict on arch/arm/mach-imx/gpc.c. And Jason Cooper's irqchip/vybrid
branch was pulled into the base as a run-time dependency.
* tag 'imx-dt-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (69 commits)
ARM: dts: hummingboard: add sgtl5000 support for Hummingboard Pro
ARM: dts: imx25-pinfunc: Add several pinfunctions
ARM: dts: vf610: fix missing irqs
ARM: dts: cubox: Map gpio-keys to gpio3 8
ARM: dts: hummingboard: Setup pwm lines
ARM: dts: hummingboard: enable PCF8523 RTC support
ARM: dts: Re-license SolidRun iMX6 platform DT GPL v2/X11
ARM: dts: imx28: add alternative pinmuxing for spi3
ARM: dts: imx6sx: Add label snvs_rtc
ARM: dts: imx6sl: Add label snvs_rtc
ARM: imx6: Warn when an old DT is detected
ARM: imx6: Allow GPC interrupts affinity to be changed
ARM: imx6qdl-sabreauto.dtsi: add max7310 support
ARM: dts: imx6sl-warp: Add BCM4330 support
ARM: dts: imx28-apf28dev: add wakeup function to user button
ARM: dts: imx28-apf28dev: fix user button polarity
ARM: dts: imx25-pinfunc: remove input values for pinfuncs without input register
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
ARM: dts: imx6sl-warp: Pass 'bus-width' property
ARM: dts: imx6qdl: disable PWMs by default
...
Pull "Clean-up for omap PRCM (Power Reset Clock Management) and interconnects" from Tony Lindgren
Patches originally from Tero Kristo <t-kristo@ti.com>.
This sets gets us into a better position for further clean-up:
- Gets PRCM code closer to being device drivers
- Allows to move the remainig clock code to drivers/clk for v4.2
- Starts enforcing interconnect hierarchy in the SoC specific .dts
files to enforce device drivers are only accesing registers in
the related hardware module
This patchset has seen quite a few revisions but did not come into
mergeable shape until recently. As other patchsets for clock specific
device drivers depend on this, it would be good to get this merged
although it's a bit late for the v4.1 merge window.
Note that as the device entries in the .dts files are moved around,
this is based on earlier non-urgent fixes to avoid a non-trivial
merge conflict.
* tag 'omap-for-v4.1/prcm-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (44 commits)
ARM: OMAP4+: control: add support for initializing control module via DT
ARM: dts: dra7: add minimal l4 bus layout with control module support
ARM: dts: omap5: add minimal l4 bus layout with control module support
ARM: OMAP4+: control: remove support for legacy pad read/write
ARM: OMAP4: display: convert display to use syscon for dsi muxing
ARM: dts: omap4: add minimal l4 bus layout with control module support
ARM: dts: am4372: add minimal l4 bus layout with control module support
ARM: dts: am43xx-epos-evm: fix pinmux node layout
ARM: dts: am33xx: add minimal l4 bus layout with control module support
ARM: dts: omap3: add minimal l4 bus layout with control module support
ARM: dts: omap24xx: add minimal l4 bus layout with control module support
ARM: OMAP2+: control: add syscon support for register accesses
ARM: OMAP2+: id: cache omap_type value
ARM: OMAP2+: control: remove API for getting control module base address
ARM: OMAP2+: clock: add low-level support for regmap
ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init
ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags
ARM: OMAP2+: CM: move SoC specific init calls within a generic API
ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility
ARM: OMAP2+: PRM: move SoC specific init calls within a generic API
...
OMAP4, OMAP5 and DRA7 now parse DT entries for control module address spaces,
and set up syscon mappings appropriately. Low level IO init is updated to
remove the legacy control module mappings for these devices also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch creates the l4_cfg and l4_wkup interconnects for OMAP5, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
omap4_ctrl_pad_readl/writel are no longer used by anybody, so remove
these. Syscon / pinctrl should be used to access the padconf area
instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The legacy control module APIs will be gone, thus convert the display
driver to use syscon. This change should eventually be moved to
display driver from the board directory.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
This patch creates the l4_cfg and l4_wkup interconnects for OMAP4, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Tony Lindgren <tony@atomide.com>
This patch creates an l4_wkup interconnect for AM43xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM nodea as the clock provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Pinmux node should be a reference to the base one, not a complete re-write
of it. Having the node like this also prevents modifying the node layout
in the base am4372.dtsi file, which is needed for control module changes.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch creates an l4_wkup interconnect for AM33xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM node as the clock provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch creates an l4_core interconnect for OMAP3, and moves some
of the generic peripherals under it. System control module nodes are
moved under this new interconnect also, and the SCM clock layout
is changed to use the renamed SCM node as the clock provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Tony Lindgren <tony@atomide.com>
This patch creates an l4 / l4-wkup interconnects for omap2420 / omap2430
SoCs, and moves some of the generic peripherals under it. System control
module nodes are moved under this new interconnect also, and the SCM
clock layout is changed to use the new SCM node as the clock provider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Control module driver needs to support syscon for register accesses, as
the DT hierarchy for control module driver is going to be changed. All
the control module related features will be moved under control module
node, including clocks, pinctrl, and generic configuration register
access. Temporary iomap is still provided very early in the boot for
access while syscon is not yet ready.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There is no need to read the register with every invocation of the function,
as the value is constant. Thus, cache the value in a static variable.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Some of the TI clock providers will be converted to use syscon, thus
low-level regmap support is needed for the clock drivers also. This
patch adds this support, which can be enabled for individual drivers
in later patches.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The compatible DT node is now passed with the prm init, so there is no
need to do node matching here again. Added a new flag to the init data
also, to detect default IRQ support for OMAP4. Also, any booting omap4
DT setup always has a PRM node, so there is no need to check against
the special case where it would be missing.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Currently some cpu_is_X checks are used to setup prm_features, however
the same can be accomplished by just passing these flags from the PRM
init data. This is done in preparation to make PRM a separate driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This gets rid of need for some exported driver APIs, and simplifies the
initialization of the CM driver. Done in preparation to make CM a
separate driver. The init data is now also passed to the SoC specific
implementations, allowing future expansion to add feature flags etc.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
PRM device instance offset is now provided through the prm_init_data.
This gets rid of some cpu_is_X / soc_is_X calls from PRM core code,
preparing for PRM to be its own separate driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This gets rid of need for some exported driver APIs, and simplifies the
initialization of the PRM driver. Done in preparation to make PRM a
separate driver. The init data is now also passed to the SoC specific
implementations, allowing future expansion to add feature flags etc.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch adds some not yet defined pinfunctions. It also adds two
comments about mistakes in the i.MX25 reference manual so it is easier
to spot the difference between reference manual and pinfunction
definitions.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
While adding the MSCM interrupt router, all interrupts have been moved
to vfxxx.dtsi again. However, some properties got lost. Readd the
missing interrupt properties.
Fixes: 97e6466ab9d0 ("ARM: dts: vf610: add Miscellaneous System Control
Module (MSCM)")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The Cubox has a recessed button between the HDMI and RJ-45 connectors
that wasn't mapped in the device tree, so I've mapped it to gpio-keys
BTN_0.
Signed-off-by: George Joseph <george.joseph@fairview5.com>
Tested-by: George Joseph <george.joseph@fairview5.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Setup pwm lines as follows -
pwm1: In case HummingBoard base carrier; this pin drives through a serial
capacitor the mono out of the audio jack.
In case HummingBoard pro the this pad can be reached by wiring to
C8 capacitors on the board.
pwm2: Setup pwm2 on gpio-1 but leave the default function of the iopad as
a gpio.
The user can change the io pad mux in user space and therefore use
this function on gpio-1 (pin number 7 on the 26 pin header).
pwm3,pwm4: unused
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
[tweaked alias for pwm pinctrl group --rmk]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It may be useful to disable the internal snvs-rtc when an external rtc is
available. This patch adds a label so that dts files can disable it.
Based on a patch from Markus Pargmann for imx6qdl.dtsi.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It may be useful to disable the internal snvs-rtc when an external rtc is
available. This patch adds a label so that dts files can disable it.
Based on a patch from Markus Pargmann for imx6qdl.dtsi.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Now that the GPC has been converted to be a full blown irqchip
(and not a mole on the side of the GIC), booting a new kernel
with an old DT is likely to result in a rough ride for the user.
This patch makes sure such a situation is promptly detected and
the user made aware that a DT update is in order.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
While converting the GPC code to a stacked irqchip, we lost the
possibility to change the CPU affinity of an interrupt routed
through the GPC.
This patch restore the expected behaviour by forwarding the
affinity setup to the underlying irqchip (GIC).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
input values are only useful for pin functions which define a input
register. This patch removes all input values of pin functions which do
not have an input configuration register.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In a second block, there is an interrupt router, which
handles the routing of the interrupts between the two CPU cores
on VF6xx variants of the SoC. However, also on single core
variants the interrupt router needs to be configured in order
to receive interrupts on the CPU's interrupt controller. Almost
all peripheral interrupts are routed through the router, hence
the MSCM module is the default interrupt parent for this SoC.
In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will be used with,
the correct parent interrupt controller has to be assigned to
the MSCM-IR node (GIC or NVIC). The driver takes care of the
parent interrupt controller specific needs (interrupt-cells).
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since PWMs are only useful if they are actually connected to an output pin,
let users enable them explicitly in their device trees where they should
also set up the pin configuration.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
All PWM users should explicitly enable the used PWMs in their device tree
so they can be disabled by default in imx6qdl.dtsi.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
All PWM users should explicitly enable the used PWMs in their device tree
so they can be disabled by default in imx6qdl.dtsi.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The PU regulator is enabled during boot, but not necessarily always-on.
It can be disabled by the generic pm domain framework when the PU power
domain is shut down. The ramp delay of 150 us might be a bit conservative,
the value is taken from the Freescale kernel.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled and a list of clocks to be enabled during powerup
for reset propagation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled, and a list of phandles to all clocks that must be
enabled during powerup for reset propagation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The chipidea driver adds an extra line of spam to the log when a
host-only chipidea instance is left set to the default of a dual role
controller.
[ 2.010873] ci_hdrc ci_hdrc.1: doesn't support gadget
Set the dr_mode property to host on all the host-only nodes
to avoid this warning.
Signed-off-by: Matt Porter <mporter@konsulko.com>
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
