If current task finish with soft timeout, the next
task in pending list will not get processing.
So, need to trigger again in mpp_task_timeout_work to
ensure that next task in pending task gets processed in time.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Iefa57c883eda81553c1b4c17be4f18c4dc83c946
Based on hardware testing, the change could improve the rising
edge and falling edge for RXCLK.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6779f2c1bcdf0e3b9aaa1553e4456cd581304302
Based on hardware testing, the change could improve signal quality for RGMII.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibba6130308f152922848687bb00c04a41efce5bc
Enable the following macros for AMP system:
CONFIG_ROCKCHIP_AMP=y
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ie8335e429d0da4414994df553351611351c24704
Workaround for FIFO clear on SLAVE mode:
A Suggest to do reset hclk domain and then do mclk
domain, especially for SLAVE mode without CLK in.
at last, recovery regmap config.
B Suggest to switch to MASTER, and then do FIFO clr,
at last, bring back to SLAVE.
Now we choose plan B here.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iac775ff092c6d16e0240459e60fc8112b54f61c6
1. Modify the polarity configuration.
2. Monitor timing changes using VMON_VMEAS/VMON_HMEAS interrupts.
3. Add sip_hdmirx_config operation, cooperate with bl31 reset
controller logic.
4. Configure the HPD low time to 1 second to enhance compatibility.
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Change-Id: I4f55e0ece74df7c9e82391bae6afb4154fec96d9
The otg wakelock should be destroyed when the device probe failed
or removed, else may cause the following kernel errors.
list_add corruption. next->prev should be prev (ffffffc01209d3c8), but
was 0000000000000000. (next=ffffff800350faf8).
------------[ cut here ]------------
kernel BUG at lib/list_debug.c:25!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
Modules linked in:
CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.10.110 #83
Hardware name: Rockchip RK3562 EVB1 LP4X V10 Board (DT)
pstate: 60400085 (nZCv daIf +PAN -UAO -TCO BTYPE=--)
pc : __list_add_valid+0x6c/0x88
lr : __list_add_valid+0x6c/0x88
[...]
Call trace:
__list_add_valid+0x7c/0x98
wakeup_source_register+0x120/0x160
wakeup_source_register+0x120/0x160
device_init_wakeup+0x60/0xf4
[...]
So add devm action to fix it.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: If54a299a694414ad759002e4f6c4187448ccdb15
1.ensure hardware is being off status when task done
2.add soft reset process for iep
3.enable hw timeout
4.disable md_pre when md_lambda == 8
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I700fffddc9a7a2c37b9790d938a243978fa3abdc
"cpu_online_mask" hasn't been cleared yet in CPUHP_AP_ONLINE_DYN stage.
So we use cpumask_any_but instead of cpumask_first.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I0a29d18869f50ac584fc545d27045f631045d568
add rkvdec link info for vdpu382 version
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I7ec36faf021de723257595f0df99cce4722442a0
Try to get the maximum PD revision which Type-C controller can
support from DT, and use this value to init the PD negotiated
revision instead of hard coded values 0x0300 (PD3.0).
This can fix at least the following two Type-C controllers issues:
1. FUSB302 failed to response PD Message "Get Source Cap Ext" if
used the default negotiated revision PD_MAX_REV (PD_REV30)
with MacBook (test on macOS 12.2.1).
2. ET7301B failed to detect the voltage status of the measured
CC pin for vRd-3.0 if used the default negotiated revision
PD_MAX_REV (PD_REV30) with some Type-C DP monitors.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I2c9bcc06ff2b3d678a6eab5013cec7f45cbda3dd
This property is used to tell the maximum USB Power Delivery
revision which Type C controller can support.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ibc0b35096ae270cd6d0e67cbdb2e5b85604f43b3
The Cortex-A76 core supports:
The Armv8.2-A extension.
The RAS extension.
The Load acquire (LDAPR) instructions introduced in the Armv8.3-A extension
The Dot Product support instructions introduced in the Armv8.4-A extension.
The PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB,
PSSBB) instructions introduced in the Armv8.5-A extension.
Disable follow ARMv8.3/4/5 features:
-CONFIG_ARM64_PTR_AUTH
-CONFIG_ARM64_AMU_EXTN
-CONFIG_ARM64_TLB_RANGE
-CONFIG_ARM64_BTI
-CONFIG_ARM64_E0PD
-CONFIG_ARCH_RANDOM
-CONFIG_ARM64_MTE
-CONFIG_ARM64_SVE
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I34b8af33b9ed64add2a5e17f6bfa4d3c7601c07f
RK3588 Cortex-A76 version is r4p0.
1188873 Fixed in r3p0.
1165522 Fixed in r3p0.
1286807 Fixed in r3p1.
1463225 Fixed in r4p0.
2054223 Cortex-A710
2067961 Neoverse-N2
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I02b3f71d6b276c6bd1bdce35d8da0838748b954a
