1. register 0x3260 should be set 0x00 in hdr mode, set 0x01 in normal mode
2. rhs1 should be 4n+1 when set hdr ae
Signed-off-by: Yiqing Zeng <zack.zeng@rock-chips.com>
Change-Id: I8e662f35e544dc75bf9506f1254bc1a4da358b58
sensor driver use reset instead of rst, so sync this.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I4d5a1bbf7db9da53a5ca6c5740ef1e1dbb8f796d
rv1126 bat ipc v10 is a demo board with battery.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I99cadefb1c649c98c3f9b3abfd816c3c28d59686
Some SoCs have different number of endpoints between the EP-IN
and EP-OUT (e.g. RK3399/RV1126 have 7 in endpoints and 6 out
endpoints), it will fail to init all of the endpoints.
In my test case, I use RV1126 dwc3 to support 3 UVC functions
at the same time, and each UVC function need one in endpoint
for control interface and one in endpoint for streaming interface,
so it needs to init 7 in endpoints (include ep0-in) in this case.
Without this patch, it will fail to init the ep7-in because
it set the wrong DWC3_DEP_BASE for ep7-in.
According to dwc3 databook, the register DALEPENA and the "USB
Endpoint Number" field of Parameter1 are doing 1:1 mapping for
endpoints, meaning physical endpoints 2 maps to logical endpoint
2:
Bit[0]: USB EP0-OUT
Bit[1]: USB EP0-IN
Bit[2]: USB EP1-OUT
Bit[3]: USB EP1-IN
...
Bit[13]: USB EP7-IN
The dwc3 driver use dep->number to index endpoint number and init
the DALEPENA and the "USB Endpoint Number" field of Parameter1.
For RV1126, it should set dep->number to 13 for EP7-IN.
But the registers DEPCMDPAR2(#n),DEPCMDPAR1(#n), DEPCMDPAR0(#n),
and DEPCMD(#n) don't 1:1 mapping for endpoints. For RV1126, it
should set #n to 12 for EP7-IN. And the event->endpoint_number
in the dwc3_endpoint_interrupt() is equal to 12 for EP7-IN.
Fixes: c2185009e2 ("usb: dwc3: gadget: fix init endpoints and resize tx fifos")
Change-Id: I0898306196f4dacf09b0de3cf4d76d9026b6315c
Signed-off-by: William Wu <william.wu@rock-chips.com>
frm start int don't be set, current & next frame start occur simultaneously
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I49f28a6d49e8a726f3f8a4c290444792a497876f
Remove prepare callback for mpp service callback
function only used in video codec link table mode.
Update task private data acquired method for mpp
service revision.
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
Change-Id: I01e908699b5e2eeb29e0a8706a3e526bf8568167
This patch add support for rv1126/rv1109 soc.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Id27ce5bd3dd5c4e4f3273e09fbebcfd6a5d5f085
This patch add cpu code parse from otp or efuse.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I550eb01725ba265d5eb47caaf1d0e66656cfb4b0
enqueue_task() may call cpufreq_task_boost() before governor is initial,
so enable_sem and speedchange_task is not initial, then do not boost.
Fixes: 2d367d61e8 (cpufreq: interactive: introduce boost cpufreq interface for task)
Change-Id: I68ec027299fa46e7749efd43b44af6e476753ac5
Signed-off-by: Liang Chen <cl@rock-chips.com>
this patch add V4L2_CID_HFLIP and V4L2_CID_VFLIP support
and fixed error in setting HDRAE_EXP
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: If92dfa4b09aff13ddf0be8498898ad8bc6a45950
We found a situation where state->visible is true but
the plane is disabled, and state->fb is null.
According to the documentation of struct drm_plane_state,
the member crtc can truly describe the plane enable/active
state. So we check state->crtc instead of plane->visible here.
Change-Id: I9f9e8912c7279c1c68c8370014b08c7ba6bae72c
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This adds support to limit frequency at multiple temperature zones, but
the frequency will be also changed by thermal framework if the device is
a cooling device.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I609cede78fce7e0a264fb961b422f05a45a7c949
Ensure the pclk is enabled when register access occurs.
Change-Id: Id108a04aed8424725dcc02dec9fe46bfc724c09b
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
There are some configs needed to update for rockchip_linux_defconfig.
As below:
1) UART number increase to 6, e.g: px30...
2) Enable HW_RANDOM_ROCKCHIP for fast ramdom number init
3) Enable some the missing configs for rk805
4) Enable ARM_ROCKCHIP_BUS_DEVFREQ config
5) Enable USB_CONFIGFS_F_UVC for UVC
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I880a4c59e40ba7b79f6f68fc39fca55919314e7b
Add the px30-evb-ddr3-v11-linux.dts for new panel on px30 evb boards.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I3f9acdd5f31c666487b1a51f611aa406ca553645
Fixes: d3d4f3e92d ("arm64: dts: rockchip: use ports to link DSI node and panel")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I25328b4ac95fc88c0bbfa64c2a0dfd33040a8f63
