The configured parameter buf, module_cfg_update will
set to 0 for user.
ISP2X_MODULE_FORCE BIT(64) for parameter buf to use.
Change-Id: I54f867b4ca50ae1ebfbee884b44bbf1a5cfc53b9
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
fix bug the first frame uv address error
when venc from 2560 * 1440 change to 1920 * 1080
uv address will be change in frame end, but ready
event from frame start. venc will make regs when
receive ready event at once.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Ib0cfd85b8455e2b68e86c39532a935c0bd2dfe27
Skipping suspend and resume for uart keeping work
Fixes: 62d96185bd (serial: 8250_dw: uart wake up)
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I3d650774dba7a785b2db167c2afd037db8efcaaa
This is a workaround to fix for uboot, which needs the phandle from
rk3308bs_cpu0_opp_table and rk3308bs_dmc_opp_table nodes to do fix.
If uboot never rely on the phandle, this patch can be reverted.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I116d578f343feeb790e7265c13b0442354164d97
Now a fixed regulator is supplied by another fixed regulator, the parent
should probe first to avoid a defer-probe error.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I270bab86ba8fa8c4389134972ee7f5bbb1bf1037
There is one Temperature Sensor for CPU on rk3308bs.
Change-Id: I297f58d476c6dd037dd203ea06b571d061e48686
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Cherry-picked from v4.19 also fix rk_tsadcv4_initialize
to rk_tsadcv2_initialize, which committed by Finley Xiao:
commit: 875a83545151 ("thermal: rockchip: Fix initialize for rk3308")
The rk_tsadcv4_initialize is used to fix channal invertion issue for
px30, but there isn't the issue on rk3308.
Change-Id: Ibf1782ca471c8ad4b14d6fd64eeb123181903adc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
There are two Temperature Sensor on px30s, channel 0 is for CPU,
channel 1 is for GPU.
set trim for px30s.
Change-Id: I25e16c8d398634d83a3611fa829ee2e9dd974538
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
When level==0(low-performance mode):
1. prefer prev_cpu for rt tasks if prev cpu is fit.
2. make sure that it saves at least 6% of the energy when
migrate tasks from little cpu to big cpu.
When level==2(high-performance mode):
1. do not use EAS path.
2. select big cpu first when system is not overutilized.
3. do not trigger load_balance() when system is not overutilized.
4. prefer prev_cpu for rt tasks if prev cpu is fit.
Test performance improvement for level==2:
1. CONFIG_ROCKCHIP_PERFORMANCE=n
EMMC Random Write(4KB) 25.44MB/s
Antutu:
Total 581266
CPU 133023
GPU 234106
MEM 103602
UX 110535
2. CONFIG_ROCKCHIP_PERFORMANCE=y and level==2
EMMC Random Write(4KB) 44.19MB/s (73.7% improvement)
Antutu:
Total 600483 (3.3% improvement)
CPU 134481 (1.1% improvement)
GPU 234678
MEM 116551 (12.5% improvement)
UX 114773 (3.8% improvement)
Change-Id: I949ac229864eb12159b886b7769e0b489345bef4
Signed-off-by: Liang Chen <cl@rock-chips.com>
The iodomain driver has been moved into soc/rockchip and it needs to be
called early before devices, set fs_initcall to it.
Change-Id: I68756377411299e3a4bacbae462ae18b8c31c072
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
RV1126 set 3.3V before regulator disable.
Do a fix to rockchip io-domain, follow this orders:
* system running state
-> io-domain vsel to 3.3V (actually is done by event-disable)
-> regulator_enable
-> vsel change according to regulator voltage
* system running state
-> regulator_disable
-> io-domain vsel to 3.3V
The bug only instance on RV1126, and tested on RV1126 EVB DDR3 V10.
Change-Id: Ic9d6b05d07b050c392e415786cf6390cc1c5aa9e
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This adds the necessary data for handling io voltage domains on the rk3308.
As interesting tidbit, the rk3308 contains one iodomain area at grf,
Change-Id: Ife72a284a8926d02ef5df7a422d41924494d0300
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
A clock driver for a arm SoC should depend on ARM, but for a arm64 SoC,
the driver should not depend on ARM64 since SoC could used as 32bit,
such as the RK3308 aarch32 platform.
Fixes: 5f3de16bb2 ("clk: rockchip: depends on CPU config")
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I9bc2c22b8c20dc6aedecbc288f551de1c0f02216
128+64KB at the beginning of RAM reserved for ATF.
128KB for pstore.
Change-Id: I1306daec44c65258ff6668f6760be4981d7ca932
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
256KB alignment is not work for (textofs & 0xf0000) > 0x40000.
Change to 1MB.
Change-Id: I9803b22d7d64a244842dcc811e47e214d247fc0c
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Sync driver with v4.4 and v4.19, support rk3308bs/px30s/rk3326s whose io
type is new called as smic type.
The smic type io configure drive strength with 3 bit, the highest bit is
from slew rate bit for the origin io type, that also means the smic io
not support slew rate setting.
The drive strength setting difference:
regval RK3308B RK3308BS
0 2mA 0mA
1 4mA 2mA
2 8mA 4mA
3 12mA 6mA
4 6mA
5 8mA
6 10mA
7 12mA
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ibcbdc06eefa819dae114a4b9adc32cdff42d32f2
This patch makes the dma-heap device support to get physical address by
DMA_HEAP_IOCTL_GET_PHYS. The sub heaps can add a support to this ops.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I1daf65f742ce48db5548aa3fb860bb3fb4e2291d
Add partital sync support for begain/end of cpu access.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I36cc7d2fffd1e22d796d429c76a990542acb8dd2
When the dmabuf attachment list is empty, do force sync with the heap
device, it is useful for partial access for cpu.
Fixes: 21f2fd663e ("dma-buf: system_heap: support cpu access partial dma-buf")
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ie266767aeb03a361e1541ba9e84f3dd027350a75
Add the function of reading efuse txlevel, if it cannot be read,
use the default value.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I1d92f139312e0ea67f96017cac2370fe00a7de31
Add the function of reading efuse bgs, if it cannot be read,
use the default value.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6895766d342407a0a0b6011f0ea121770008e291
The internal context is automatically canceled after calling commit
by default.
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: I40f14fa0bddb95475a5cc76911a30df2ea1e122c
For some rockchip SOCs, Power Domain protection is supported
in AMP system.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I1e0cbde37df44dba466fc580b7f67d0053d09e3d
Parse and enable irq wakeup if the "wakeup-source" property was present.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I21b974d65dc02c1f3bd5f0e52a1372367b77a6e4
Mailbox irq can be used as a wakeup source when the "wakeup-source"
property was present.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I11df0a1ced263214a8204c4944343e21d5935454
As the opp voltage may be changed if enable pvtm, it's better to use
rockchip,high-temp-max-freq.
Change-Id: If480a6ffa23efa9213b3b809f3cde320ce2a5ddd
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change the maximum frequency of cpu to 1104MHz.
Change-Id: I4dddd81907dc3bb7dd55c0a8eda41b16990ca203
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
